i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
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5.5.2 Power Results for ADPCM Decoder Bench Mark<br />
Table 5-18 summarizes the power consumed by the chip for every stripe in the SuperCISC<br />
reconfigurable hardware fabric design when the ADPCM (Adaptive Differential Pulse Code<br />
Modulation) decoder bench mark was run on the fabric. The pre-layout power consumption of<br />
the chip was 0.917mW and the post-layout power consumption was 1.168mW.<br />
Stripe<br />
Number<br />
Table 5-18: ADPCM Decoder Post Layout Power Simulation<br />
Pre-Layout<br />
Power (uW)<br />
ALU Stripe MUX Stripe<br />
Post-Layout<br />
Power(uW)<br />
Pre-Layout<br />
Power (uW)<br />
Post-Layout<br />
Power(uW)<br />
S1 81.3 101.9 29.35 41.75<br />
S2 62.69 75.06 25.48 37.41<br />
S3 66.42 80.55 27.78 41.62<br />
S4 51.45 61.23 24.75 34.72<br />
S5 50.17 60.9 23.86 35.46<br />
S6 43.38 52.16 18.9 27.41<br />
S7 41.86 50.89 17.9 26.88<br />
S8 35.37 42.55 17.27 24.29<br />
S9 48.63 57.21 26.61 38.42<br />
S10 31.19 34.65 19.68 28.95<br />
S11 36.02 41.96 12.64 18.61<br />
S12 22.66 25.72 10.23 14.49<br />
S13 21.29 24.03 15.09 21.08<br />
S14 26.89 32.6 10.52 14.75<br />
S15 6.849 6.901 0.1199 0.1199<br />
S16 2.307 2.307 0.1199 0.1199<br />
S17 2.307 2.307 0.1199 0.1199<br />
S18 2.307 2.307 3.536 6.929<br />
Total<br />
Power<br />
(uW) 633.09 755.232 283.9557 413.1287<br />
74