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definitions, metal layer resistance and capacitance. For defining the standard cell library, LEF
contains the abstract layout of the cells, cell dimensions, layout of pins and pin capacitances.
However, LEF does not contain information about the internal netlist of the cells [32].
Design Exchange Format (DEF)
DEF is also an ASCII data format from Cadence for representing the physical
layout.
The DEF data represents
the netlist and the circuit layout information. DEF is used in
conjunction with LEF to represent the complete
physical layout of the integrated circuit being
designed [33]
Cadence Timing Library Format (TLF)
TLF is an ASCII representation of the timing and power parameters associated with
any standard cell in a particular technology [34]. The TLF file contains
timing models and data
to calculate I/O path delays, timing check values and interconnect delays
[34]. A TLF file is used
as an input to the Cadence tools.
Synopsys Liberty File Format (.lib)
Synopsys Liberty Format is an industry standard way to represent information
about the standard
cell library for a particular technology. The .lib file contains descriptions of the standard cell’s
input and output pins, logical function of every cell, timing
information specific to cell delays,
rise and fall transitions times at the outputs, energy information specific to the energy consumed
when the input makes a rise transition or a fall transition and cell’s leakage power. In addition to
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