i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

To meet the design requirement of having an undelayed falling edge, the current source
required to discharge Q has been replaced with an NMOS transistor. The NMOS transistor M17
gets enabled when D input makes a transition from a logic high to a logic low. The NMOS
transistor discharges node Q at a fast rate and hence the delay element does not have a delay on
the falling edge of the signal.
Input Vctrl of transistor M11 acts as the current source for the delay element. The signal
Vctrl is generated from a constant gm based current source circuit and the transistor M11 mirrors
the current. The current source used in the design is based on a 100nA current source.
6.5.1 Programmability
For a 20X18 ALU configuration of the hardware fabric, there would be 360 ALU nodes
(assuming homogeneous ALU configuration).The delay elements that are used can have value of
4ns, 5ns and 7ns, which totals to 3 delay elements per ALU node. Use of 3 delay elements per
ALU node makes the number of delay elements used in the fabric to be around 3*360. The use
of so many delay elements is prohibitive from an area perspective. So the idea of using a
programmable delay element based on scaling the current source helps to overcome the overhead
in having multiple delay elements. This programmability reduces the number of delay elements
from 1080 to 360.
One possible configuration would be to scale the input current mirror transistor
connecting to signal Vtrl by having multiple PMOS transistors in parallel with enable switches
connected to them in series. The major drawback behind this application is from the fact that the
sizes of the input current mirror transistors are large. So, when the D input is off, charge gets
stored on the drains of the large current mirror transistors and when the D input gets turned ON
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