i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

6.5.3 Parasitic Extraction of the Delay Element
To annotate the design with parasitics from the layout, parasitic extraction was done using
Mentor Graphics Calibre xRC. The parasitic capacitance annotated HSPICE netlist was used for
characterizing the complete design. The tool annotates both the wire capacitance to ground as
well as the coupling capacitance between nets.
6.5.4 Cell Characterization and HSPICE Post-Processing
The objective of building the delay element is to characterize its power characteristics for various
delay values. The characterized data can be transformed into Synopsys Liberty Format to be used
in the standard cell based ASIC design flow. The HSPICE post-processing script automates the
cell characterization procedure. Appendix B contains the HSPICE post-processing script written
in Perl to automate the cell characterization. The delay element cell was characterized for various
values of load capacitance and input transition times. The HSPICE post-processor reads the
HSPICE netlist and changes the load capacitance and transition times appropriately and the
measurement commands suited for the simulation. The netlist is simulated in HSPICE after the
post-processing step. The measurement data is written into a “netlist.mt0” file by HSPICE. The
simulated data is read and the data format is changed to be readable by the user.
Three different versions of the standard cell were created with different drive strengths.
These delay elements differ only in the output buffer used to drive the load. The first version of
the delay element has the capability to drive a 80fF load. The next has the capability to drive a
160fF load and third has the capability to drive a 640fF load. Figure 6-25 shows the layout of a
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