i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

9.0 CONCLUSION
For this thesis, I have completed the placement and routing of the SuperCISC reconfigurable
hardware fabric including the ALU, MUX and the FINALMUX Stripe in the IBM 0.13um
CMOS technology using Cadence SoC Encounter. The post place and route SDF and parasitic
SPEF file have been generated from the design to be annotated in the power analysis flow using
Prime Power. The post parasitic annotated power analysis numbers have been generated for a
variety of benchmarks.
A
CMOS thyristor based delay element with a programmable feature has been
implemented in the IBM 0.13um CMOS process. The improved delay element
consumes very
little on-state and sub-threshold leakage power. The design has been characterized for use as a
standard cell in an ASIC design flow as well as in the SuperCISC design flow to minimize the
glitching power consumption.
An EEPROM design using a 0.35um, 20V technology has been implemented to show
that power gating can be used to increase the memory size with a minimum power overhead for
use in the SuperCISC architecture. The macromodel of the FLOTOX transistor has been
implemented in HSPICE. The design shows that the power gated memory block consumes very
little static power and hence can be used to increase the size of the memory.
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