i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

that, the file also contains environmental statistics such as certain process information, operating
temperature and supply voltage variations [35].
Standard Delay Format (SDF)
Standard Delay Format (SDF) files store timing information generated by the EDA tools
for a particular design. The data in the SDF is represented in a tool-independent way and can
describe module path delays, device delays, interconnect and port delays. It can also include
timing constraints such as set-up, hold and skew. The SDF file can be used at various stages in
the design process. An SDF generated after synthesis represents the pre-payout timing
information in
layout timing information.
the design while an SDF generated after placement and routing contains post-
The SDF file is typically generated by a timing calculator based on the design netlist and
pre or post layout information. The SDF data that is generated is used by the annotator which
uses the SDF information for performing various timing and power analysis [36].
Standard Parasitic Extraction Format
(SPEF)
The
SPEF is an IEEE Standard for representing the parasitic information in the design in
an ASCII format. The SPEF specification
is a part of the 1481-1999 IEEE Standard for
Integrated Circuit(IC) Power and Delay Calculation System standard [37]. The SPEF contains
parasitic resistance, capacitance and inductance of wires on the chip. The SPEF information can
be used by the delay calculation engine to generate timing data or can be used by an analysis tool
to estimate power after the design has been annotated with the parasitic information.
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