i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

The write power consumption dominates the read power consumption because of the high
voltage used to program the device. The major power consuming component during a write
operation is the high voltage charge pump which generates the voltage required to erase and
program the devices [24]. Many circuit level optimizations have been proposed by [24] to keep
the charge pump power low during the write operation. Apart from the charge pump, power is
consumed in charging and discharging the word lines and the control gate line to Vpp during the
erase operation and in charging the bit lines to Vpp during a write operation, where Vpp is the
high voltage supplied by the charge pump.
During a write operation, the choice of the programming voltage is dominated by the
EEPROM process rather than by the designer. Hence, to keep the dynamic power low it becomes
necessary to keep the charging capacitance low at a fixed operating frequency. With the increase
in size of the memory from 128 bytes to 256
bytes, for example, an architectural decision to
increase the number of rows or the number of columns is required. Increasing the number of
columns increases the page width, which in turn necessitates an increase in the current required
to program the device. This design choice mandates an increase in the size of the charge pump
and hence a proportionate increase in power. On the other hand, an increase in the number of
rows, increases the bit line capacitance that needs to be charged during a write operation. Hence,
scaling the memory while keeping the dynamic power low is a design challenge. Hence, a power
gated memory solution enables to expand the memory size with minimal penalty because the
expanded memory block is disabled and is enabled only when required.
144