i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

8.0 POWER GATED EEPROM DESIGN
High power consumption has always been an issue with EEPROM design because of the
inherent nature of the FLOTOX memory processes that use a high voltage to program these
devices. Many circuit level optimizations have been made in the past to reduce the power
consumption of the basic EEPROM block. The thesis proposes an architectural level power
optimization using power gating technique to increase the size of the memory while keeping the
active power low. The power-gated memory design minimizes both the dynamic and leakage
power associated with memories. Simulations have been performed using HSPICE models for a
0.35um CMOS process.
Our solution is to build a hierarchical low-power memory block using power-gating
technique for the non-accessed memory block. The concept of multi-block architecture [28] is a
common low power technique used in memory design. However, the use of power gating
reduces the power consumption si gnificantly as compared to other sleep mode techniques.
8.1 ARCHITECTURE OF THE POWER GATED MEMORY
A ``power enable'' PMOS device is added in series with the memory block as shown in
Figure 8-1. This allows only the block that is actually addressed to be powered, while the
remaining blocks remain disconnected from power. As the EEPROM uses both a high voltage
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