i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

7.2.7 Memory Bank Architecture
Figure 7-21 shows the schematic of the memory bank architecture that has been implemented.
The implementation has two power multiplexer configurations, wordline power multiplexer and
control gate power multiplexer. The wordline power multiplexer is used to multiplex between the
high voltage (Vpp), boosted voltage (Vdd_boost) and ground (gnd). This is because the wordline
output is Vpp during erase and program operations, Vdd_boost during a read operation and gnd
when the memory is disabled. The wordline is asserted for the appropriate row that gets selected
from the address decoding action of the row address decoder. The level shifter in the wordline
path asserts the appropriate voltages only to the wordline that is activated. All other wordlines
are disconnected and are not enabled.
The
control gate power multiplexer is used to multiplex Vpp, Vdd and gnd voltages to
the control gate of the EEPROM cells. The multiplexer outputs Vpp when the device needs to be
erased , Vdd during a read operation and
gnd when the device needs to be programmed or when
the device is disabled. The Vpp to the control gate multiplexer is generated by the erase ramp
generator circuit to meet the appropriate ramp conditions.
The column data latch is used to latch the data value that needs to be written into the
memory. Depending on the latched value, the column latch outputs either a Vpp or a tri-state
output. The Vpp to the column latch is generated by the program ramp generator. The column
select lines “col0,”, “col1” are used to select the appropriate column during a read operation. The
column select lines are activated by a column address decoder. The sense amplifier finally reads
the voltage on the bit lines and decides the logic value of the voltage that is being read out. The
“bl_s” generator circuit is used to generate the precharge voltages that are necessary to precharge
the sources of the EEPROM cells.
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