i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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Table 5-22: Laplace Post Layout Power Simulation .................................................................... 78 Table 8-1: Power Gated Memory Simulation Results ................................................................ 148 Table D 1: Characterization data for 4ns delay element using 160fF buffer...............................184 Table D 2: Characterization data for 4ns delay element using 640fF buffer .............................. 185 Table D 3: Characterization data for 4ns delay element using 80fF buffer ................................ 186 Table D 4: Characterization data for a 5ns delay element using 160fF buffer ........................... 187 Table D 5: Characterization data for a 5ns delay element using 640fF buffer ........................... 188 Table D 6: Characterization data for a 5ns delay element using 80fF buffer ............................. 190 Table D 7: Characterization data for a 7ns delay element using 160fF buffer ........................... 191 Table D 8: Characterization data for a 7ns delay element using 640fF buffer ........................... 192 Table D 9: Characterization data for a 7ns delay element using 80fF buffer ............................. 193 x
LIST OF FIGURES Figure 1-1: SuperCISC Reconfigurable Hardware Fabric Triangle ............................................... 2 Figure 1-2: SuperCISC RHF System Integration Diagram ............................................................ 5 Figure 2-1: Architecture of SuperCISC Reconfigurable Hardware Fabric .................................... 8 Figure 2-2: ALU Logical Diagram ............................................................................................... 10 Figure 2-3: 5:1 MUX Interconnect Structure ................................................................................ 11 Figure 2-4: FINALMUX Stripe Logical Diagram ........................................................................ 12 Figure 3-1: Power Dissipation Terminology Tree ........................................................................ 14 Figure 3-2: Schematic of an Inverter ............................................................................................ 16 Figure 3-3: Prime Power Event Based Simulation Flow .............................................................. 18 Figure 3-4: Leakage Power definition of a NAND Standard Cell ................................................ 21 Figure 3-5: NLPM definition of Internal Power ........................................................................... 23 Figure 3-6: Rise Power Measurement window ............................................................................. 24 Figure 3-7: HSPICE Rise Power Calculation command .............................................................. 25 Figure 3-8: Fall Power Measurement window .............................................................................. 25 Figure 3-9: On-state leakage Power Measurement window ......................................................... 26 Figure 3-10: Off-state leakage Power Measurement window ...................................................... 27 Figure 4-1 : Typical ASIC Design Flow ....................................................................................... 29 Figure 4-2: ASIC Physical Design Flow ...................................................................................... 31 Figure 4-3: Floorplan specifications ............................................................................................. 32 Figure 4-4: ALU Stripe Floor plan ............................................................................................... 32 Figure 4-5: Power Planning .......................................................................................................... 33 xi
Page 1 and 2: A PHYSICAL IMPLEMENTATION WITH CUST
Page 3 and 4: A PHYSICAL IMPLEMENTATION WITH CUST
Page 5 and 6: 4.0 ASIC DESIGN FLOW ..............
Page 7 and 8: 6.5.5 Characterization Results for
Page 9: LIST OF TABLES Table 5-1: ALU Modul
Page 13 and 14: Figure 5-20: BIGFABRIC Logical Diag
Page 15 and 16: Figure 7-4: EEPROM Erase Physical O
Page 17 and 18: ACKNOWLEDGEMENTS “Many, O Jehovah
Page 19 and 20: 1.0 INTRODUCTION Technological adva
Page 21 and 22: Property) block. The physical desig
Page 23 and 24: the thesis proposes a power gated m
Page 25 and 26: 2.0 SUPERCISC RECONFIGURABLE HARDWA
Page 27 and 28: The specifications of the hardware
Page 29 and 30: INP2 selects from ALU1, ALU2, ALU3
Page 31 and 32: 3.0 POWER ESTIMATION The need for e
Page 33 and 34: 3.1.1 Static Power Consumption Stat
Page 35 and 36: Internal Power Internal Power is th
Page 37 and 38: Switching activity Generation Switc
Page 39 and 40: Figure 3-4: Leakage Power definitio
Page 41 and 42: The entire array contains informati
Page 43 and 44: 3.3.2 Calculation of Fall Power Fig
Page 45 and 46: Figure 3-10: Off-state leakage Powe
Page 47 and 48: Figure 4-1 : Typical ASIC Design Fl
Page 49 and 50: Figure 4-2: ASIC Physical Design Fl
Page 51 and 52: 4.1.2 Powerplanning Power planning
Page 53 and 54: created in the design. Routing feed
Page 55 and 56: 4.1.7 Routing Once the standard cel
Page 57 and 58: Table 5-1: ALU Module Specification
Page 59 and 60: Table 5-2 shows the important speci
Page 61 and 62:
the basic parameters are specified,
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direction have to be aligned on the
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ALU Stripe Pin Assignment The “ib
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5.2.1 MUX Module Specifications As
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Figure 5-12: MUX Stripe Logical Dia
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MUX initialization routine The MUX
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Table 5-10: MUX Stripe Pin Placemen
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Figure 5-15: FINALMUX Module Logica
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Table 5-12: Final MUX Stripe Specif
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pins in the FINALMUX stripe is plac
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larger system. Figure 5-22 shows th
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 5-22: Place and Routed BIGFA
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BIGFABRIC Stripe Pin Assignment As
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The SPEF file can be generated usin
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5.5.1 Power Results for ADPCM Encod
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5.5.3 Power Results for IDCT Row Be
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5.5.5 Power Results for Sobel Bench
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6.0 DELAY ELEMENTS FOR LOW POWER FA
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Transmission gate with Schmitt Trig
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PMOS transistors have their gate in
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output normally. The signal integri
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m-Transistor Cascaded Inverter This
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6.2 LOW POWER FABRIC USING DELAY EL
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The use of delay elements in the ha
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6.3.2 Dynamic Triggering Scheme A d
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Figure 6-16 shows the shunt current
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td1 is the delay in discharging nod
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δt is the regeneration time of the
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transistors, they are active low si
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delay elements are enabled on a log
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charge sharing happens between the
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Figure 6-23: AND gate to generate D
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uffer with a drive capacity of 640f
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Cell Rise Delay The Cell Rise Delay
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Fall Transition Time The time taken
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6.5.6 Characterization Results for
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7.0 EEPROM CIRCUIT DESIGN EEPROM (E
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7.1.1 Erase Operation Figure 7-3: I
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7.1.2 Write Operation Figure 7-6: I
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Figure 7-9: IV Characteristics of a
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The current source IFN, resistor RT
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Figure 7-11: HSPICE Description of
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7.2.1 Ramp Generator The ramp gener
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7.2.4 Column Latch for Bitlines inp
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7.2.5 Power Multiplexer Figure 7-16
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The inverter pair connected to the
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7.2.7 Memory Bank Architecture Figu
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7.2.8 Memory Bank Simulation Figure
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(Vpp) and a normal voltage (Vdd), t
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8.1.2 Dynamic Decoder The address d
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8.3 POWER-ON RESET One problem with
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Figure 8-6 shows the modified charg
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To study the impact of the power co
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9.0 CONCLUSION For this thesis, I h
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definitions, metal layer resistance
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APPENDIX B element standard cell ch
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$k=-1; $j=-1; $i=-1; foreach $ load
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$FALL_START_8 = $OFFSET8 + $ONTIME;
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if ($#rise_power_6 == -1) { # $modi
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$modified_spice_array[$i] = $temp2;
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@fall_power_9 = grep(/fall_power9/,
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print MEASHANDLE $_; print ENERGYHA
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} print MEASHANDLE " "; print ENERG
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set VAL [expr "$NUMBER_OF_MODULES_P
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set DIE_WIDTH_STRIPE [expr {($MODUL
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#*************************PLACING i
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preassignPin stripe $PIN_NAME -loc
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set X_LOC [expr {($X _LOC -( 31*$OU
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#Module related details set NUMBER_
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set X_LOC 0 set Y_LOC 41.2 for {set
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Table D 1 (Continued) 506.232fF 0.0
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121.344fF 0.076ns 0.4634 0.2277 570
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Table D 5 (Continued) 9.48 0. 516 0
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Table D 7: Characterization data fo
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Transi tion Table D 9: Characteriza
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[13] M.F. Aburdene, J. Zheng, and R
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i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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