i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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while() { $original_spice_array[$i] = $_; $modified_spice_array[$i] = $_; $i++; } close (IN); open(MEASHANDLE,">measurement.out"); open(ENERGYHANDLE,">energy.out"); print MEASHANDLE "CAPACITIVE_LOAD TRANSTION_TIME RISE_POWER1 RISE_POWER2 RISE_POWER3 RISE_POWER4 RISE_POWER5 RISE_POWER6 RISE_POWER7 RISE_POWER8 RISE_POWER9 RISE_POWER10 RISE_POWER11 RISE_POWER12 FALL_POWER1 FALL_POWER2 FALL_POWER3 FALL_POWER4 FALL_POWER5 FALL_POWER6 FALL_POWER7 FALL_POWER8 FALL_POWER9 FALL_POWER10 FALL_POWER11 FALL_POWER12 RISE_TR1 RISE_TR2 RISE_TR3 RISE_TR4 RISE_TR5 RISE_TR6 RISE_TR7 RISE_TR8 RISE_TR9 RISE_TR10 RISE_TR11 RISE_TR12 FALL_TR1 FALL_TR2 FALL_TR3 FALL_TR4 FALL_TR5 FALL_TR6 FALL_TR7 FALL_TR8 FALL_TR9 FALL_TR10 FALL_TR11 FALL_TR12 CELL_RISE_DELAY1 CELL_RISE_DELAY2 CELL_RISE_DELAY3 CELL_RISE_DELAY4 CELL_RISE_DELAY5 CELL_RISE_DELAY6 CELL_RISE_DELAY7 CELL_RISE_DELAY8 CELL_RISE_DELAY9 CELL_RISE_DELAY10 CELL_RISE_DELAY11 CELL_RISE_DELAY12 CELL_FALL_DELAY_1 CELL_FALL_DELAY2 CELL_FALL_DELAY3 CELL_FALL_DELAY4 CELL_FALL_DELAY5 CELL_FALL_DELAY6 CELL_FALL_DELAY7 CELL_FALL_DELAY8 CELL_FALL_DELAY9 CELL_FALL_DELAY10 CELL_FALL_DELAY11 CELL_FALL_DELAY12 ILEAK_HI1 ILEAK_HI2 ILEAK_HI3 ILEAK_HI4 ILEAK_HI5 ILEAK_HI6 ILEAK_HI7 ILEAK_HI8 ILEAK_HI9 ILEAK_HI10 ILEAK_HI11 ILEAK_HI12 ILEAK_LO1 ILEAK_LO2 ILEAK_LO3 LEAK_LO4 ILEAK_LO5 ILEAK_LO6 ILEAK_LO7 ILEAK_LO8 ILEAK_LO9 ILEAK_LO10 ILEAK_LO11 ILEAK_LO12 REFERENCE_CURRENT\n"; print ENERGYHANDLE "CAPACITIVE_LOAD TRANSTION_TIME RISE_POWER1 RISE_POWER2 RISE_POWER3 RISE_POWER4 RISE_POWER5 RISE_POWER6 RISE_POWER7 RISE_POWER8 RISE_POWER9 RISE_POWER10 RISE_POWER11 RISE_POWER12 FALL_POWER1 FALL_POWER2 FALL_POWER3 FALL_POWER4 FALL_POWER5 FALL_POWER6 FALL_POWER7 FALL_POWER8 FALL_POWER9 FALL_POWER10 FALL_POWER11 FALL_POWER12 RISE_TR1 RISE_TR2 RISE_TR3 RISE_TR4 RISE_TR5 RISE_TR6 RISE_TR7 RISE_TR8 RISE_TR9 RISE_TR10 RISE_TR11 RISE_TR12 FALL_TR1 FALL_TR2 FALL_TR3 FALL_TR4 FALL_TR5 FALL_TR6 FALL_TR7 FALL_TR8 FALL_TR9 FALL_TR10 FALL_TR11 FALL_TR12 CELL_RISE_DELAY1 CELL_RISE_DELAY2 CELL_RISE_DELAY3 CELL_RISE_DELAY4 CELL_RISE_DELAY5 CELL_RISE_DELAY6 CELL_RISE_DELAY7 CELL_RISE_DELAY8 CELL_RISE_DELAY9 CELL_RISE_DELAY10 CELL_RISE_DELAY11 CELL_RISE_DELAY12 CELL_FALL_DELAY_1 CELL_FALL_DELAY2 CELL_FALL_DELAY3 CELL_FALL_DELAY4 CELL_FALL_DELAY5 CELL_FALL_DELAY6 CELL_FALL_DELAY7 CELL_FALL_DELAY8 CELL_FALL_DELAY9 CELL_FALL_DELAY10 CELL_FALL_DELAY11 CELL_FALL_DELAY12 ILEAK_HI1 ILEAK_HI2 ILEAK_HI3 ILEAK_HI4 ILEAK_HI5 ILEAK_HI6 ILEAK_HI7 ILEAK_HI8 ILEAK_HI9 ILEAK_HI10 ILEAK_HI11 ILEAK_HI12 ILEAK_LO1 ILEAK_LO2 ILEAK_LO3 LEAK_LO4 ILEAK_LO5 ILEAK_LO6 ILEAK_LO7 ILEAK_LO8 ILEAK_LO9 ILEAK_LO10 ILEAK_LO11 ILEAK_LO12 BUF_RISE_DELAY1 BUF_RISE_DELAY2 BUF_RISE_DELAY3 BUF_RISE_DELAY4 BUF_RISE_DELAY5 BUF_RISE_DELAY6 BUF_RISE_DELAY7 BUF_RISE_DELAY8 BUF_RISE_DELAY9 BUF_RISE_DELAY10 BUF_RISE_DELAY11 BUF_RISE_DELAY12 BUF_FALL_DELAY1 BUF_FALL_DELAY2 BUF_FALL_DELAY3 BUF_FALL_DELAY4 BUF_FALL_DELAY5 BUF_FALL_DELAY6 BUF_FALL_DELAY7 BUF_FALL_DELAY8 BUF_FALL_DELAY9 BUF_FALL_DELAY10 BUF_FALL_DELAY11 BUF_FALL_DELAY12 \n"; 156
$k=-1; $j=-1; $i=-1; foreach $ load (@loadarray) { print "HELLO WORLD1\n"; $k++; $j=-1; $i=-1; foreach $searchstring (@modified_spice_array) { $i++; @cap = grep(/cload/,$searchstring); if ($#cap == -1) { } else { @temp1 = split(/\s/,$searchstring); $temp1[3] = $loadarray[$k]; $temp2 = join(" ",@temp1); $modified_spice_array[$i] = $temp2."\n"; } } foreach $tr (@trarray) { $j++; $i=-1; print "CAPACITANCE : $load "; print "TRANSIENT TIME : $tr\n"; $PW = 50e-9; $PERIOD = 100e-9; $ONTIME = $PW + $tr; $OFFTIME = $PERIOD - $ONTIME; $OFFSET1 = 10e-6; $OFFSET2 = 11e-6; $OFFSET3 = 12e-6; $OFFSET4 = 13e-6; $OFFSET5 = 14e-6; $OFFSET6 = 15e-6; $OFFSET7 = 16e-6; $OFFSET8 = 17e-6; $OFFSET9 = 18e-6; $OFFSET10 = 19e-6; $OFFSET11 = 20e-6; $OFFSET12 = 21e-6; 157
Page 1 and 2:
A PHYSICAL IMPLEMENTATION WITH CUST
Page 3 and 4:
A PHYSICAL IMPLEMENTATION WITH CUST
Page 5 and 6:
4.0 ASIC DESIGN FLOW ..............
Page 7 and 8:
6.5.5 Characterization Results for
Page 9 and 10:
LIST OF TABLES Table 5-1: ALU Modul
Page 11 and 12:
LIST OF FIGURES Figure 1-1: SuperCI
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 7-4: EEPROM Erase Physical O
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ACKNOWLEDGEMENTS “Many, O Jehovah
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1.0 INTRODUCTION Technological adva
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Property) block. The physical desig
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the thesis proposes a power gated m
Page 25 and 26:
2.0 SUPERCISC RECONFIGURABLE HARDWA
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The specifications of the hardware
Page 29 and 30:
INP2 selects from ALU1, ALU2, ALU3
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3.0 POWER ESTIMATION The need for e
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3.1.1 Static Power Consumption Stat
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Internal Power Internal Power is th
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Switching activity Generation Switc
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Figure 3-4: Leakage Power definitio
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The entire array contains informati
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3.3.2 Calculation of Fall Power Fig
Page 45 and 46:
Figure 3-10: Off-state leakage Powe
Page 47 and 48:
Figure 4-1 : Typical ASIC Design Fl
Page 49 and 50:
Figure 4-2: ASIC Physical Design Fl
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4.1.2 Powerplanning Power planning
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created in the design. Routing feed
Page 55 and 56:
4.1.7 Routing Once the standard cel
Page 57 and 58:
Table 5-1: ALU Module Specification
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Table 5-2 shows the important speci
Page 61 and 62:
the basic parameters are specified,
Page 63 and 64:
direction have to be aligned on the
Page 65 and 66:
ALU Stripe Pin Assignment The “ib
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5.2.1 MUX Module Specifications As
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Figure 5-12: MUX Stripe Logical Dia
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MUX initialization routine The MUX
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Table 5-10: MUX Stripe Pin Placemen
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Figure 5-15: FINALMUX Module Logica
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Table 5-12: Final MUX Stripe Specif
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pins in the FINALMUX stripe is plac
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larger system. Figure 5-22 shows th
Page 83 and 84:
Figure 5-20: BIGFABRIC Logical Diag
Page 85 and 86:
Figure 5-22: Place and Routed BIGFA
Page 87 and 88:
BIGFABRIC Stripe Pin Assignment As
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The SPEF file can be generated usin
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5.5.1 Power Results for ADPCM Encod
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5.5.3 Power Results for IDCT Row Be
Page 95 and 96:
5.5.5 Power Results for Sobel Bench
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6.0 DELAY ELEMENTS FOR LOW POWER FA
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Transmission gate with Schmitt Trig
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PMOS transistors have their gate in
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output normally. The signal integri
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m-Transistor Cascaded Inverter This
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6.2 LOW POWER FABRIC USING DELAY EL
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The use of delay elements in the ha
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6.3.2 Dynamic Triggering Scheme A d
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Figure 6-16 shows the shunt current
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td1 is the delay in discharging nod
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δt is the regeneration time of the
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transistors, they are active low si
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delay elements are enabled on a log
Page 123 and 124: charge sharing happens between the
Page 125 and 126: Figure 6-23: AND gate to generate D
Page 127 and 128: uffer with a drive capacity of 640f
Page 129 and 130: Cell Rise Delay The Cell Rise Delay
Page 131 and 132: Fall Transition Time The time taken
Page 133 and 134: 6.5.6 Characterization Results for
Page 135 and 136: 7.0 EEPROM CIRCUIT DESIGN EEPROM (E
Page 137 and 138: 7.1.1 Erase Operation Figure 7-3: I
Page 139 and 140: 7.1.2 Write Operation Figure 7-6: I
Page 141 and 142: Figure 7-9: IV Characteristics of a
Page 143 and 144: The current source IFN, resistor RT
Page 145 and 146: Figure 7-11: HSPICE Description of
Page 147 and 148: 7.2.1 Ramp Generator The ramp gener
Page 149 and 150: 7.2.4 Column Latch for Bitlines inp
Page 151 and 152: 7.2.5 Power Multiplexer Figure 7-16
Page 153 and 154: The inverter pair connected to the
Page 155 and 156: 7.2.7 Memory Bank Architecture Figu
Page 157 and 158: 7.2.8 Memory Bank Simulation Figure
Page 159 and 160: (Vpp) and a normal voltage (Vdd), t
Page 161 and 162: 8.1.2 Dynamic Decoder The address d
Page 163 and 164: 8.3 POWER-ON RESET One problem with
Page 165 and 166: Figure 8-6 shows the modified charg
Page 167 and 168: To study the impact of the power co
Page 169 and 170: 9.0 CONCLUSION For this thesis, I h
Page 171 and 172: definitions, metal layer resistance
Page 173: APPENDIX B element standard cell ch
Page 177 and 178: $FALL_START_8 = $OFFSET8 + $ONTIME;
Page 179 and 180: if ($#rise_power_6 == -1) { # $modi
Page 181 and 182: $modified_spice_array[$i] = $temp2;
Page 183 and 184: @fall_power_9 = grep(/fall_power9/,
Page 185 and 186: print MEASHANDLE $_; print ENERGYHA
Page 187 and 188: } print MEASHANDLE " "; print ENERG
Page 189 and 190: set VAL [expr "$NUMBER_OF_MODULES_P
Page 191 and 192: set DIE_WIDTH_STRIPE [expr {($MODUL
Page 193 and 194: #*************************PLACING i
Page 195 and 196: preassignPin stripe $PIN_NAME -loc
Page 197 and 198: set X_LOC [expr {($X _LOC -( 31*$OU
Page 199 and 200: #Module related details set NUMBER_
Page 201 and 202: set X_LOC 0 set Y_LOC 41.2 for {set
Page 203 and 204: Table D 1 (Continued) 506.232fF 0.0
Page 205 and 206: 121.344fF 0.076ns 0.4634 0.2277 570
Page 207 and 208: Table D 5 (Continued) 9.48 0. 516 0
Page 209 and 210: Table D 7: Characterization data fo
Page 211 and 212: Transi tion Table D 9: Characteriza
Page 213 and 214: [13] M.F. Aburdene, J. Zheng, and R
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