1996 Electronics Industry Environmental Roadmap - Civil and ...

Emerging Technologies
intense light through the mask and through a series of reducing lenses, exposing the
photoresist with the mask pattern. Precise alignment of the wafer to the mask prior to
exposure is critical. Most alignment tools are fully automatic.
Developing: The wafer is then “developed” so that any exposed photoresist is removed,
and the wafer is baked to harden the remaining photoresist pattern. It is then exposed to a
chemical solution or plasma (gas discharge) so that areas not covered by the hardened
photoresist are fully opened to expose underlying materials. At this point patterned
photoresist is used to selectively cover areas on the wafer and allow removal of materials
outside the photoresist areas (such as metallization or oxides) and to provide areas for
selective deposition (such as doping).
Doping: Atoms with either one less electron than silicon (such as boron) or one more
(such as phosphorous) are introduced into the areas exposed by the developing process to
alter the electrical character of the silicon. These areas are called P-type (boron) or Ntype
(phosphorous) to reflect their conducting characteristics.
Dielectric Deposition and Metallization: Following oxidation and doping steps, contacts
and interconnects are formed to create individual transistors and the interconnections between
transistors (for implementing complex multi-transistor circuits). These contacts
and interconnections are formed through repeated sequences of dielectric deposition,
dielectric patterning, conductor deposition and conductor patterning.
Current semiconductor fabrication includes as many as five metal layers separated by dielectric
layers to “wire up” the collection of transistors and implement the full IC circuitry. After the last
metal layer is patterned, a final dielectric layer (passivation) is deposited to protect the circuit
from damage and contamination. Openings are etched in this film to allow access to the top layer
of metal by electrical probes and wire bonds. Figure 6-1 provides a generalized representation of
the IC manufacturing sequence.
Environmental Impacts: Each of the major process steps used in IC manufacturing involves
some combination of energy use, material consumption, and material waste. Table 6-1 illustrates
some example environmental issues resulting from the more common process steps as outlined
above.
Process Environmental Issues/Impact
Silicon crystal ingot growth Energy consumption
Silicon wafer preparation Waste stream from chemo-mechanical polishing
Thermal oxide growth Energy consumption
Resist application Waste resist from spin-on-process (often 90% of
total) and solvent vapors
Resist develop Developer waste and dissolved resist
Resist strip Waste stream from dissolved resist (gaseous or
liquid waste) and wafer cleaning step
Conductor deposition including
polysilicon and silicides
Gaseous waste
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