1996 Electronics Industry Environmental Roadmap - Civil and ...

Appendix A
SIA/SEMATECH In selecting a new architecture, process designers should worry as
much about the reproducibility of each manufacturing step as about
devices and structures. This issue is addressed through suitable
qualification procedures of the equipment.
The roadmap notes the importance of technology computer-aideddesign
(technology modeling) and states that CAD tools therefore need
timely deployment on a hierarchical basis for optimum integrated
technology design, including high speed and low power issues.
Predictive modeling and simulation of materials, processes and devices
are critical to timely and economic technology development.
To design a high reliability process, better DFM and CAD techniques
are needed. Wafer (device) level electrical tests, chip sort, KGD, and
class yield analysis methods must be improved to meet feedback
control standards for final product quality in the factory. Other
challenges relate to the high integration density that creates power
dissipation limitations and the interconnect bottlenecks on chips and at
the I/O interface.
Roadmap notes that key requirements for improved process
integration, device and structure design are improvements in on-chip
and off-chip frequency, power density, and V dd reduction. In the area
of tools for design, the roadmap notes that tools for simulating
performance and reliability require improvement, short-flow
methodology should be developed, improved tools for KGD and BIST
are needed, and improved strategies for yield analysis and defect
allocation.
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