1996 Electronics Industry Environmental Roadmap - Civil and ...

Appendix A
SIA/SEMATECH As CMOS technology is scaled to the 0.10 µm size/1.0 V supply
regime, the trade-offs among performance, leakage, and reliability
become increasingly constrictive. Two routes are suggested:
evolutionary devices fabricated using a silicon technology or
revolutionary devices, possibly using alternative devices and materials.
Traditional device and structure design procedures are incorporated in
CAD. The full activity of process design includes design for
manufacturability, reliability, performance (DFM, DFR, DFP, etc.).
CAD is a means of linking data from various sources to enable the
design of an optimum integrated process and device design.”
With high performance 2.5-V devices, on-chip clock speeds of 300
MHz or higher should be feasible
Increasing the productivity of factories requires new factory designs
for specific applications plus high adaptability to change as the pace of
technology change accelerates. This results in the need to integrate
disciplines that, to date, have been largely practiced in isolation.
[NOTE: Illustration indicates that ES&H is one of these disciplines]
There is a need to integrate the fabrication facility and its associated
suppliers throughout all steps of semiconductor device manufacturing
from product development through product shipment.
Six areas covered in this Roadmap section are: Facilities infrastructure,
Modeling and Simulation, Product and Material Handling,
Manufacturing Information and Control Systems; Process and
Equipment Control, and Human Resources (skills development)
Modularization and standardization of the equipment, building
systems, and other factory components are vital to improve flexibility
and reduce transition costs and time from generation to generation.
Key considerations in facilities’ infrastructure: specialty gas systems,
fluid delivery systems, factory environment, building systems,
correlation (between direct process materials and process results),
metrology.
Of paramount importance is developing a fundamental understanding
of the relationships between the contaminants in chemicals, gases, and
water and the surface concentrations of these contaminants on the
wafer as a result of the process. Unless progress is made on modeling
the transfer function for in situ contaminants to surface contaminants
on silicon, factories will incur cost penalty for using ultrapure
materials.
In the next 15 years, key changes in the semiconductor wafer factor
architecture will include additional environmental emission controls at
both the factory level and the local tool level.
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