1996 Electronics Industry Environmental Roadmap - Civil and ...

Appendix A
SIA/SEMATECH The increasing aspect ratios of contacted, vias, and metal spaces
necessitate conformal-coating solutions (e.g., CVD or chemical vapor
deposition for barrier, adhesion, and plug formation.
Gap fill technology for metal spaces is required
Higher conductivity wiring (e.g., copper) and lower dielectric constant
insulators will help reduce RC delays
In each process/tool, designed-in features should include minimized
harmful emissions, particle avoidance, sensors, GEM communications,
and control systems to meet the cost of ownership requirements
Look for alternatives to fluorine and halocarbons: used to dry etch
multi-layer Al-based interconnects
Need techniques to remove oxides and metals from dilute waste
streams.
New organic ILDs should be screened to see if these materials are EPA
approved for sale in semiconductor operations
Revolutionary breakthroughs might be superconductivity materials,
optical interconnections, or use of biological materials (but not likely
before the 2010 window.
(continued)
NEMI One key implication of current trends is that bare die will begin to
dominate over time. This will be driven by the movement to multichip
modules and chip-on-board for a wide variety of systems as movement
to unpackaged devices will continue to the point that direct chip attach
will be the dominant device-level packaging technology used. Solderbased
direct-chip attach processes and multi-layered printed wiring
boards and ceramic or silicon substrates will likely be used for systems
requiring high reliability, while adhesive-based direct-chip attach
processes and thin printed wiring boards or flex circuits will likely be
used where cost is the dominant factor in system design.
Required core technology competencies in packaging include:
integrated modeling and simulation; advanced manufacturing
equipment; advanced materials; thermal management technologies;
high-density, low-noise substrates; cost-effective high quality
environmentally benign manufacturing technologies; and
environmental protection technology.
Anticipation in packaging is 300 to 400 mm diameter wafer by 2001,
approximately 0.2 µm thick.
Key technology options include direct-chip-attach, multi-chip modules
and known good-dye, PCMCIA cards and ball grid array packaging.
The roadmap anticipates lead-use legislation, and recommends the
establishment of a focused environmentally conscious manufacturing
program.
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