1996 Electronics Industry Environmental Roadmap - Civil and ...

Appendix A
SIA/SEMATECH Over the time span encompassed by the roadmap, the complexity of
chips and systems will grow so dramatically that new approaches based
on far more powerful and interoperable tools will be needed to handle
the design and test processes.
Already, in many cases, system level integration is limited by existing
CAD tools and their inability to let the designer work smoothly up and
down the levels of abstraction from device details to product
functionality.
Ideally, design will be done using an integrated tool suite that gives the
designer the power to create products starting from customer
specifications and working down to the details of wafer fabrication and
factory economics.
The ideal solution for the design environment would be a formal
database management system used by all tools. This solution will start
with common access interfaces and formal approaches for mapping
information between different representations and continue through
research directed at more formal DBMS solutions.
Low power is an increasingly critical need for portable and mobile
computing and communication devices. Good progress has been made
in the past year, and, in the near term, standard logic synthesis methods
can be adapted to create viable solutions. However, their quality relies
heavily on accurate power estimators that are still lacking.
Report emphasizes the need for higher level synthesis with emphasis
on improved optimization of constrained parameters.
Compute-intensive simulation for verifying system and chip
functionality must be replaced by formal analysis and verification
methodologies.
As performance demands increase further, IC level cell[?] libraries will
need to be redesigned rapidly to support fine-grain speed-power tuning.
(The report also notes that the trends to be considered are emerging
product styles such as field programmable devices, mixed signal
systems, and aggressive packaging strategies.)
The challenge in design is managing the exploding complexity. To
provide the dramatic improvement necessary in the design process as
the complexity of the chips and systems increases, two key paradigm
shifts can be identified: (1) point tools giving way to self-consistent
top down design, and (2) piecemeal solutions giving way to
hierarchical modeling and analysis.
In the area of design, the second across-the-board critical issue is that
of standards. Interoperability and related software tool and information
standards must be improved and their acceptance by industry, both
users and suppliers, as well as the universities and government
organizations, needs to be accelerated.
Drivers for the improvements needed in the near term in design and
test include the need for more accurate but predictive capabilities at the
detail level and the continuous drive for performance, power reduction,
and minimum silicon real estate for the extremely complex devices and
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systems. They must also be strongly coupled into the synthesis and test
process.
(continued)