2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Figure 33: Nominal Slew Rate for t IH (Command and Address – Clock) CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V SS DC to V REF region Hold slew rate rising signal 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating tIS tIH tIS tIH Nominal slew rate �TR VREF(DC) - VIL(DC)max Hold slew rate = falling signal = �TR Nominal slew rate DC to V REF region Note: 1. The clock and the strobe are drawn on different time scales. �TF V IH(DC)min - V REF(DC) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. �TF
Figure 34: Tangent Line for t IS (Command and Address – Clock) CK CK# DQS# DQS V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(DC)max V SS Nominal line V REF to AC region �TF 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating t IS tIH tIS tIH Tangent line tVAC Nominal line Setup slew rate rising signal = Setup slew rate falling signal = �TR t VAC Tangent line V REF to AC region Tangent line (V IH(DC)min - V REF(DC) ) �TR Tangent line (V REF(DC) - V IL(AC)max ) Note: 1. The clock and the strobe are drawn on different time scales. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. �TF
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 85 and 86: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 95 and 96: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101: Figure 32: Nominal Slew Rate and t
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
Page 143 and 144: Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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