2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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equired to program the correct value of write recovery, which is calculated by dividing t WR (ns) by t CK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup ( t WR [ns]/ t CK [ns]). Precharge Power-Down (Precharge PD) CAS Latency (CL) Figure 52: READ Latency CK# CK Command DQS, DQS# DQ CK# CK Command DQS, DQS# DQ The precharge power-down (PD) bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down, providing a lower standby current mode; however, t XPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, t XP must be satisfied when exiting (see Power-Down Mode (page 181)). The CL is defined by MR0[6:4], as shown in Figure 51 (page 136). CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14. DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m.Table 52 (page 72) through Table 55 (page 75) indicate the CLs supported at various operating frequencies. T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP AL = 0, CL = 6 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP AL = 0, CL = 8 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) DI n DI n + 1 DI n + 2 Transitioning Data DI n + 3 DI n + 4 DI n Don’t Care Notes: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal t DQSCK and nominal t DSDQ. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Mode Register 1 (MR1) Figure 53: Mode Register 1 (MR1) Definition M16 M15 Mode Register 0 0 Mode register set 0 (MR0) 0 1 Mode register set 1 (MR1) 1 0 Mode register set 2 (MR2) 1 1 Mode register set 3 (MR3) DLL ENABLE/DISABLE The mode register 1 (MR1) controls additional features and functions not available in the other mode registers: DLL ENABLE/DISABLE, output drive strength, OUTPUT ENA- BLE/DISABLE (Q OFF), TDQS ENABLE/DISABLE (x8 configuration only), on-die termination (ODT) resistance value RTT,nom, WRITE LEVELING, and posted CAS additive latency (AL). These features and functions are controlled via the bits shown in the figure below. The MR1 register is programmed via the MRS command and retains the stored information until it is reprogrammed, RESET# goes LOW, or the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is reprogrammed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) Address bus 14 13 12 11 0 Q Off 10 9 8 7 6 5 WL 4 3 2 1 0 AL RTT Mode register 1 (MR1) M0 DLL Enable 0 Enable (normal) 1 Disable M5 Output Drive Strength 0 0 1 1 RZQ/6 (40� NOM) RZQ/7 (34� NOM) Reserved Reserved 1 15 1 0 TDQS RTT ODS DLL M12 Q Off 0 Enabled 1 Disabled 1 17 0 16 0 RTT ODS M1 M7 0 1 Write Leveling Disable (normal) Enable 0 1 0 1 M4 M3 Additive Latency (AL) 0 0 Disabled (AL = 0) 0 1 AL = CL - 1 1 0 AL = CL - 2 1 1 Reserved 1 0 M11 TDQS 0 Disabled 1 Enabled 1 01 RTT,nom (ODT) 2 Non-Writes RTT,nom disabled RZQ/4 (60� NOM) RTT,nom (ODT) RZQ/2 (120� NOM) RZQ/6 (40� NOM) RZQ/12 (20� NOM) RZQ/8 (30� NOM) Reserved Reserved 3 M9 M6 M2 0 0 0 0 0 1 Writes RTT,nom disabled RZQ/4 (60� NOM) 0 1 0 RZQ/2 (120� NOM) 0 1 1 RZQ/6 (40� NOM) 1 0 0 n/a 1 0 1 n/a 1 1 0 Reserved 1 1 1 Reserved Notes: 1. MR1[17, 14, 13, 10, 8] are reserved for future use and must be programmed to 0. 2. During write leveling, if MR1[7] and MR1[12] are 1, then all R TT,nom values are available for use. 3. During write leveling, if MR1[7] is 1, but MR1[12] is 0, then only R TT,nom write values are available for use. The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command (see Figure 53 (page 139)). The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation, after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Page 95 and 96: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137: Table 77: Burst Order Burst Length
Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
Page 143 and 144: Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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