2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Figure 56: CAS WRITE Latency CK# CK Command DQS, DQS# DQ T0 T1 ACTIVE n WRITE n t RCD (MIN) T2 NOP NOP AL = 5 T6 T11 T12 WL = AL + CWL = 11 NOP CWL = 6 NOP DI n Indicates break in time scale DI n + 1 T13 NOP DI n + 2 Transitioning Data DI n + 3 T14 NOP Don’t Care AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled, the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1x refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a case temperature ( TC) of 85°C while in self refresh, unless the user enables the SRT function when TC is between 85°C and 95°C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to 2x when TC exceeds 85°C. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions for normal TC (85°C) only, meaning that if ASR is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 180)). SELF REFRESH TEMPERATURE (SRT) 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1x refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a TC of 85°C while in self refresh mode, unless the user enables ASR. When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regardless of TC. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions for normal TC (85°C) only, meaning that if SRT is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 180)). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
SRT versus ASR 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) If the normal TC limit of 85°C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95°C is needed, the user is required to provide a 2x refresh rate during manual refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2x rate. SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is performed at the 2x refresh rate regardless of the case temperature. ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1x and 2x over the supported temperature range. One other disadvantage of ASR is the DRAM cannot always switch from a 1x to 2x refresh rate at an exact TC of 85°C. Although the DRAM will support data integrity when it switches from a 1x to 2x refresh rate, it may switch at a temperature lower than 85°C. Since only one mode is necessary, SRT and ASR cannot be enabled at the same time. Dynamic On-Die Termination (ODT) The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected for the dynamic ODT resistance RTT(WR). This new DDR3 SDRAM feature enables the ODT termination resistance value to change without issuing an MRS command, essentially changing the ODT termination on-the-fly. With dynamic ODT (RTT(WR)) enabled, the DRAM switches from nominal ODT (RTT,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst, and subsequently switches back to normal ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, the RTT,nom value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcwn4, ODTLcwn8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If normal ODT (RTT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of one another. Dynamic ODT is not available during write leveling mode, regardless of the state of ODT (RTT,nom). For details on dynamic ODT operation, refer to On-Die Termination (ODT) (page 191). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Page 93 and 94: PDF: 09005aef826aaadc Micron Techno
Page 95 and 96: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
Page 143: Mode Register 2 (MR2) Figure 55: Mo
Page 147 and 148: Figure 58: MPR Block Diagram Memory
Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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