2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 161 � 2006 Micron Technology, Inc. All rights reserved.
Figure 71: READ (BC4) to WRITE (BC4) OTF
CK#
CK
Command 1
Address 2
DQS, DQS#
DQ3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
READ
Bank,
Col n
NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
READ-to-WRITE command delay = RL + t CCD/2 + 2 t CK - WL
RL = 5
Bank,
Col b
t RPRE
DO n
DO
n + 1
DO
n + 2
WL = 5
t RPST
DO
n + 3
t WPRE
DI
n
DI
n + 1
DI
n + 2
t BL = 4 clocks
DI
n + 3
t WPST
Transitioning Data
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Figure 72: READ to PRECHARGE (BL8)
CK#
CK
Command READ
NOP
NOP NOP NOP PRE
NOP NOP
Address
DQS, DQS#
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
Bank a,
Col n
t RAS
t RTP
Bank a,
(or all)
t WR
t WTR
Transitioning Data
Don’t Care
NOP NOP NOP NOP NOP ACT NOP NOP NOP NOP
DO n
DO
n + 1
t RP
DO
n + 2
DO
n + 3
DO
n + 4
DO
n + 5
DO
n + 6
DO
n + 7
Bank a,
Row b
Don’t Care
2Gb: x4, x8, x16 DDR3 SDRAM
READ Operation