2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 164 � 2006 Micron Technology, Inc. All rights reserved. Figure 76: Data Output Timing – t DQSQ and Data Valid Window CK# CK Command 1 Address 2 DQS, DQS# DQ3 (last data valid) DQ3 (first data no longer valid) All DQ collectively T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Bank, Col n RL = AL + CL t DQSQ (MAX) t LZDQ (MIN) t RPRE t DQSQ (MAX) t RPST tQH tQH DO n DO n + 1 DO n + 2 DO n + 3 DO n + 4 DO n + 5 DO n + 6 DO n + 7 DO n DO n + 1 DO n + 2 DO n + 3 DO n + 4 DO n + 5 DO n + 6 DO n + 7 DO n DO n + 1 DO n + 2 DO n + 3 Data valid Data valid DO n + 4 DO n + 5 DO n + 6 DO n + 7 t HZDQ (MAX) Don’t Care Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. 3. DO n = data-out from column n. 4. BL8, RL = 5 (AL = 0, CL = 5). 5. Output timings are referenced to V DDQ/2 and DLL on and locked. 6. t DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within a burst. 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation
Figure 77: Data Strobe Timing – READs CK CK# DQS, DQS# early strobe DQS, DQS# late strobe t LZDQS (MIN) t HZ and t LZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving t HZDQS and t HZDQ, or begins driving t LZDQS, t LZDQ. Figure 78 (page 166) shows a method of calculating the point when the device is no longer driving t HZDQS and t HZDQ, or begins driving t LZDQS, t LZDQ, by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters t LZDQS, t LZDQ, t HZDQS, and t HZDQ are defined as single-ended. t RPRE t LZDQS (MAX) RL measured to this point t DQSCK (MIN) t DQSCK (MIN) t DQSCK (MIN) t DQSCK (MIN) t QSH t QSL t QSH t QSL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 t RPRE t DQSCK (MAX) t DQSCK (MAX) t DQSCK (MAX) t DQSCK (MAX) t QSH t QSL t QSH t QSL 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation T0 T1 T2 T3 T4 T5 T6 t HZDQS (MIN) t RPST Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 t HZDQS (MAX) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 165 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. t RPST
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
Page 143 and 144: Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
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Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
Page 195 and 196: Table 89: Mode Registers for R TT(W
Page 199 and 200: Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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