2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 90 � 2006 Micron Technology, Inc. All rights reserved. Table 58: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table DDR3-1866 DDR3-2133 Parameter Symbol Min Max Min Max Unit Notes ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables (page 72) for tRC ns 31, 43 ACTIVATE-to-ACTIVATE 1KB page size tRRD MIN = greater of 4CK or 5ns CK 31 minimum command period 2KB page size MIN = greater of 4CK or 6ns CK 31 Four ACTIVATE 1KB page size tFAW 27 – 25 – ns 31 windows 2KB page size 35 – 35 – ns 31 Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32, 33 Delay from start of internal WRITE transaction to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/ tCK (AVG); MAX = n/a CK MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK ZQCL command: Long calibration time Calibration Timing POWER-UP and RE- tZQinit MIN = n/a SET operation MAX = max(512nCK, 640ns) Normal operation tZQoper MIN = n/a MAX = max(256nCK, 320ns) ZQCS command: Short calibration time MIN = n/a MAX = max(64nCK, 80ns) tZQCS Initialization and Reset Timing CK Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Begin power supply ramp to power supplies stable tVDDPR MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35 CK CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions
PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 91 � 2006 Micron Technology, Inc. All rights reserved. Table 58: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table DDR3-1866 DDR3-2133 Parameter Symbol Min Refresh Timing Max Min Max Unit Notes REFRESH-to-ACTIVATE or REFRESH tRFC – 1Gb MIN = 110; MAX = 70,200 ns command period tRFC – 2Gb MIN = 160; MAX = 70,200 ns tRFC – 4Gb MIN = 260; MAX = 70,200 ns tRFC – 8Gb MIN = 350; MAX = 70,200 ns Maximum refresh TC � 85°C – 64 (1X) ms 36 period TC > 85°C 32 (2X) ms 36 Maximum average TC � 85°C tREFI 7.8 (64ms/8192) μs 36 periodic refresh TC > 85°C 3.9 (32ms/8192) μs 36 Exit self refresh to commands not requiring a locked DLL tXS Self Refresh Timing MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a tXSDLL MIN = tDLLK (MIN); CK 28 locked DLL MAX = n/a Minimum CKE low pulse width for self refresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or powerdown entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, power-down exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a Power-Down Timing CK CKE MIN pulse width tCKE (MIN) Greater of 3CK or 5ns CK Command pass disable delay tCPDED MIN = 2; MAX = n/a CK Power-down entry to power-down exit tim- tPD MIN = tCKE (MIN); CK ing MAX = 9 * tREFI Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 85 and 86: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Page 95 and 96: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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