2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
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ACTIVATE Operation<br />
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row<br />
in that bank must be opened (activated). This is accomplished via the ACTIVATE command,<br />
which selects both the bank and the row to be activated.<br />
After a row is opened with an ACTIVATE command, a READ or WRITE command may<br />
be issued to that row, subject to the tRCD specification. However, if the additive latency<br />
is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the DRAM enables a READ or WRITE command to be issued<br />
after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement<br />
that (ACTIVATE-to-READ/WRITE) + AL � tRCD (MIN) (see Posted CAS Additive<br />
Latency). tRCD (MIN) should be divided by the clock period and rounded up to the next<br />
whole number to determine the earliest clock edge after the ACTIVATE command on<br />
which a READ or WRITE command can be entered. The same procedure is used to convert<br />
other specification limits from time units to clock cycles.<br />
When at least one bank is open, any READ-to-READ command delay or WRITE-to-<br />
WRITE command delay is restricted to tCCD (MIN).<br />
A subsequent ACTIVATE command to a different row in the same bank can only be issued<br />
after the previous active row has been closed (precharged). The minimum time interval<br />
between successive ACTIVATE commands to the same bank is defined by tRC. A subsequent ACTIVATE command to another bank can be issued while the first bank is<br />
being accessed, which results in a reduction of total row-access overhead. The minimum<br />
time interval between successive ACTIVATE commands to different banks is defined<br />
by tRRD. No more than four bank ACTIVATE commands may be issued in a given<br />
tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter<br />
applies, regardless of the number of banks already opened or closed.<br />
Figure 64: Example: Meeting t RRD (MIN) and t RCD (MIN)<br />
CK#<br />
CK<br />
Command<br />
Address<br />
BA[2:0]<br />
T0 T1<br />
T2 T3 T4 T5 T8 T9<br />
ACT NOP<br />
NOP ACT NOP<br />
NOP NOP NOP NOP<br />
RD/WR<br />
Row Row Col<br />
Bank x Bank y Bank y<br />
t RRD<br />
<strong>2Gb</strong>: <strong>x4</strong>, <strong>x8</strong>, <strong>x16</strong> <strong>DDR3</strong> <strong>SDRAM</strong><br />
ACTIVATE Operation<br />
t RCD<br />
Indicates break<br />
in time scale<br />
T10 T11<br />
Don’t Care<br />
PDF: 09005aef826aaadc<br />
<strong>2Gb</strong>_<strong>DDR3</strong>_<strong>SDRAM</strong>.pdf – Rev. P 2/12 EN 155 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
� 2006 <strong>Micron</strong> Technology, Inc. All rights reserved.