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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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- Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
- Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
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- Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
- Page 147 and 148: Figure 58: MPR Block Diagram Memory
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- Page 153 and 154: MPR Read Predefined Pattern The pre
- Page 155 and 156: ACTIVATE Operation Before any READ
- Page 157 and 158: READ Operation Figure 66: READ Late
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- Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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- Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
- Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
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- Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
- Page 177 and 178: Figure 93: Data Input Timing DQS, D
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- Page 181 and 182: Power-Down Mode Power-down is synch
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- Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
- Page 191 and 192: On-Die Termination (ODT) Figure 107
- Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
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- Page 199 and 200: Synchronous ODT Mode ODT Latency an
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