2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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AC Overshoot/Undershoot Specification Table 26: Control and Address Pins Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Maximum peak amplitude allowed for overshoot area (see Figure 14) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 15) Maximum overshoot area above VDD (see Figure 14) Maximum undershoot area below VSS (see Figure 15) Table 27: Clock, Data, Strobe, and Mask Pins 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Maximum peak amplitude allowed for overshoot area (see Figure 14) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 15) Maximum overshoot area above VDD/VDDQ (see Figure 14) Maximum undershoot area below VSS/VSSQ (see Figure 15) Figure 14: Overshoot Figure 15: Undershoot Volts (V) V DD /V DDQ Volts (V) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns V SS /V SSQ Maximum amplitude Time (ns) Maximum amplitude 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Time (ns) Overshoot area Undershoot area PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC Parameter/Condition Symbol Min Max Unit Notes Differential input voltage logic high - slew VIH,diff 200 n/a mV 4 Differential input voltage logic low - slew VIL,diff n/a –200 mV 4 Differential input voltage logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV 5 Differential input voltage logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC)-VREF) mV 6 Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# VIX VREF(DC) - 150 VREF(DC) + 150 mV 4, 7 Differential input crossing voltage relative to VDD/2 for CK, CK# VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 4, 7, 8 Single-ended high level for strobes VSEH VDDQ/2 + 175 VDDQ mV 5 Single-ended high level for CK, CK# VDD/2 + 175 VDD mV 5 Single-ended low level for strobes VSEL VSSQ VDDQ/2 - 175 mV 6 Single-ended low level for CK, CK# VSS VDD/2 - 175 mV 6 Notes: 1. Clock is referenced to V DD and V SS. Data strobe is referenced to V DDQ and V SSQ. 2. Reference is V REFCA(DC) for clock and V REFDQ(DC) for strobe. 3. Differential input slew rate = 2 V/ns 4. Defines slew rate reference points, relative to input crossing voltages. 5. Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable. 6. Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable. 7. The typical value of V IX(AC) is expected to be about 0.5 × V DD of the transmitting device, and V IX(AC) is expected to track variations in V DD. V IX(AC) indicates the voltage at which differential input signals must cross. 8. The V IX extended range (±175mV) is allowed only for the clock; this V IX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing V SEL, V SEH of at least V DD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. 9. V IX must provide 25mV (single-ended) of the voltages separation. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47: Figure 13: Input Signal 0.925V 0.85
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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