2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Figure 54: READ Latency (AL = 5, CL = 6) BC4 CK# CK Command DQS, DQS# DQ T0 T1 ACTIVE n internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 143)). Examples of READ and WRITE latencies are shown in Figure 54 (page 142) and Figure 55 (page 143). READ n t RCD (MIN) T2 NOP NOP AL = 5 CL = 6 T6 T11 T12 RL = AL + CL = 11 NOP 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) NOP DO n Indicates break in time scale DO n + 1 T13 NOP DO n + 2 Transitioning Data DO n + 3 T14 NOP Don’t Care PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Mode Register 2 (MR2) Figure 55: Mode Register 2 (MR2) Definition The mode register 2 (MR2) controls additional features and functions not available in the other mode registers. These addional functions are CAS WRITE latency (CWL), AU- TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (R TT(WR)). These functions are controlled via the bits shown in the figure below. MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is reprogrammed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time t MRD and t MOD before initiating a subsequent operation. M16 M15 0 0 0 1 1 0 1 1 CAS WRITE Latency (CWL) Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) M10 M9 0 0 0 1 1 0 1 1 BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 0 01 17 16 0 1 1 Dynamic ODT (R TT(WR) ) RTT(WR) disabled RZQ/4 (60� NOM) RZQ/2 (120� NOM) Reserved 13 0 1 12 11 10 9 8 7 6 5 4 3 2 1 0 ASR CWL 2 01 01 01 01 01 01 RTT(WR) SRT M7 Self Refresh Temperature 0 Normal (0°C to 85°C) 1 Extended (0°C to 95°C) Auto Self Refresh M6 (Optional) 0 Disabled: Manual 1 Enabled: Automatic 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) Address bus Mode register 2 (MR2) CAS Write Latency (CWL) 5 CK ( tCK � 2.5ns) 6 CK (2.5ns > tCK � 1.875ns) 7 CK (1.875ns > tCK � 1.5ns) 8 CK (1.5ns > tCK � 1.25ns) 9 CK (1.25ns > tCK � 1.07ns) 10 CK (1.071ns > t M5 M4 M3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 CK � 0.938ns) 1 1 0 Reserved 1 1 1 Reserved Notes: 1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 2. On die revision A, ASR is not available; MR2[6] must be programmed to 0 and, if operating in self refresh mode above 85°C, MR2[7] (SRT) must be used. CAS write latency (CWL) is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 55). The overall WRITE latency (WL) is equal to CWL + AL (Figure 53 (page 139)). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Page 91 and 92: PDF: 09005aef826aaadc Micron Techno
Page 95 and 96: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
Page 141: On-Die Termination (ODT) WRITE LEVE
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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