2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 160 � 2006 Micron Technology, Inc. All rights reserved.
Figure 69: Nonconsecutive READ Bursts
CK#
CK
DQS, DQS#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
Command READ NOP
NOP NOP NOP READ
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Address
DQ
Bank a,
Col n
CL = 8
Bank a,
Col b
Notes: 1. AL = 0, RL = 8.
2. DO n (or b) = data-out from column n (or column b).
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
Figure 70: READ (BL8) to WRITE (BL8)
CK#
CK
DO n
CL = 8
DO b
Transitioning Data
Transitioning Data
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
Command1 READ NOP NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP
DQS, DQS#
DQ3
READ-to-WRITE command delay = RL + t CCD + 2 t CK - WL
Address2 Bank,
Bank,
Col n
Col b
RL = 5
t RPRE
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DO
n + 4
DO
n + 5
DO
n + 6
WL = 5
t RPST
DO
n + 7
t WPRE
DI
n
DI
n + 1
DI
n + 2
t BL = 4 clocks
DI
n + 3
DI
n + 4
DI
n + 5
DI
n + 6
DI
n + 7
t WPST
t WR
t WR
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Don’t Care
2Gb: x4, x8, x16 DDR3 SDRAM
READ Operation