2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 82 � 2006 Micron Technology, Inc. All rights reserved. Table 57: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes WRITE with auto BL8 (OTF, MRS) tWRAP- MIN = WL + 4 + WR + 1 CK precharge command to BC4OTF DEN power-down entry BC4MRS tWRAP- DEN MIN = WL + 2 + WR + 1 Power-Down Exit Timing CK DLL on, any valid command, or DLL off to tXP MIN = greater of 3CK or 7.5ns; MIN = greater of 3CK or 6ns; CK commands not requiring locked DLL MAX = n/a MAX = n/a Precharge power-down with DLL off to commands requiring a locked DLL tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a ODT Timing CK 28 RTT synchronous turn-on delay ODTLon CWL + AL - 2CK CK 38 RTT synchronous turn-off delay ODTLoff CWL + AL - 2CK CK 40 RTT turn-on from ODTL on reference tAON –400 400 –300 300 –250 250 –225 225 ps 23, 38 RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 39, 40 Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD MIN = 2; MAX = 8.5 ns 38 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 2; MAX = 8.5 ns 40 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a Dynamic ODT Timing CK RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 39 Write Leveling Timing First DQS, DQS# rising edge tWLMRD 40 – 40 – 40 – 40 – CK DQS, DQS# delay tWLDQSEN 25 – 25 – 25 – 25 – CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 325 – 245 – 195 – 165 – ps 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions
PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 83 � 2006 Micron Technology, Inc. All rights reserved. Table 57: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 325 – 245 – 195 – 165 – ps Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
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Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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