2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Table 56: DDR3-2133 Speed Bins DDR3-2133 Speed Bin -093 1 CL- t RCD- t RP 14-14-14 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Parameter Symbol Min Max Unit Notes Internal READ command to first data tAA 13.09 20 ACTIVATE to internal READ or WRITE delay time tRCD 13.09 – ns PRECHARGE command period tRP 13.09 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.13 – ns ACTIVATE-to-PRECHARGE command period tRAS 33 9 x tREFI ns 2 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875
PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 77 � 2006 Micron Technology, Inc. All rights reserved. Electrical Characteristics and AC Operating Conditions Table 57: Electrical Characteristics and AC Operating Conditions Notes 1–8 apply to the entire table Parameter Symbol t CK DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Min Max Min Max Min Max Min Max Clock Timing Unit Notes Clock period average: TC � 85°C 8 7800 8 7800 8 7800 8 7800 ns 9, 42 DLL disable mode TC = >85°C to 95°C (DLL_DIS) 8 3900 8 3900 8 3900 8 3900 ns 42 Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables (page 72) for tCK range allowed ns 10, 11 High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12 Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12 Clock period jitter DLL locked tJITper –100 100 –90 90 –80 80 –70 70 ps 13 DLL locking tJITper,lck –90 90 –80 80 –70 70 –60 60 ps 13 Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper MAX ps Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) 14 Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) 15 Cycle-to-cycle jitter DLL locked tJITcc 200 180 160 140 ps 16 DLL locking tJITcc,lck 180 160 140 120 ps 16 Cumulative error across 2 cycles tERR2per –147 147 –132 132 –118 118 –103 103 ps 17 3 cycles tERR3per –175 175 –157 157 –140 140 –122 122 ps 17 4 cycles tERR4per –194 194 –175 175 –155 155 –136 136 ps 17 5 cycles tERR5per –209 209 –188 188 –168 168 –147 147 ps 17 6 cycles tERR6per –222 222 –200 200 –177 177 –155 155 ps 17 7 cycles tERR7per –232 232 –209 209 –186 186 –163 163 ps 17 8 cycles tERR8per –241 241 –217 217 –193 193 –169 169 ps 17 9 cycles tERR9per –249 249 –224 224 –200 200 –175 175 ps 17 10 cycles tERR10per –257 257 –231 231 –205 205 –180 180 ps 17 11 cycles tERR11per –263 263 –237 237 –210 210 –184 184 ps 17 12 cycles tERR12per –269 269 –242 242 –215 215 –188 188 ps 17 n = 13, 14 . . . 49, 50 tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN ps 17 cycles tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75: Table 55: DDR3-1866 Speed Bins DDR3
Page 79 and 80: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
Page 113 and 114: Figure 39: Tangent Line for t DH (D
Page 115 and 116: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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