2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 31 and Figure 20. The nominal slew rate for a rising signal is defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max. Table 31: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Measured Input Edge From To CK and DQS reference Calculation Rising V IL,diff,max V IH,diff,min VIH,diff,min - V IL,diff,max �TR diff Falling V IH,diff,min V IL,diff,max VIH,diff,min - V IL,diff,max �TF diff Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Differential input voltage (DQS, DQS#; CK, CK#) �TF diff 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC �TR diff V IH,diff,min 0 V IL,diff,max PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
ODT Characteristics Figure 21: ODT Levels and I-V Characteristics The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values and a functional representation are listed in Table 32 and Table 33 (page 56). The individual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows: • RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off • RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off To other circuitry such as RCV, . . . Chip in termination mode ODT I PU R TT(PU) R TT(PD) Table 32: On-Die Termination DC Electrical Characteristics I PD V DDQ I OUT = I PD - I PU Parameter/Condition Symbol Min Nom Max Unit Notes RTT effective impedance RTT(EFF) See Table 33 (page 56) 1, 2 Deviation of VM with respect to VDDQ/2 �VM –5 5 % 1, 2, 3 Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (V DDQ = V DD, V SSQ = V SS). Refer to ODT Sensitivity (page 57) if either the temperature or voltage changes after calibration. 2. Measurement definition for R TT: Apply V IH(AC) to pin under test and measure current I[V IH(AC)], then apply V IL(AC) to pin under test and measure current I[V IL(AC)]: R TT = V IH(AC) - V IL(AC) I(V IH(AC) ) - I(V IL(AC) ) I OUT DQ V OUT V SSQ 3. Measure voltage (VM) at the tested pin with no load: �VM = 2 × VM VDDQ – 1 × 100 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics 4. For IT and AT devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (T C). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53: Figure 19: Nominal Slew Rate Defini
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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