2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb: x4, x8, x16 DDR3 SDRAM Features Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 187 Figure 104: MRS Command to Power-Down Entry ......................................................................................... 188 Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 188 Figure 106: RESET Sequence ......................................................................................................................... 190 Figure 107: On-Die Termination ................................................................................................................... 191 Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 196 Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 196 Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 197 Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 198 Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 198 Figure 113: Synchronous ODT ...................................................................................................................... 200 Figure 114: Synchronous ODT (BC4) ............................................................................................................. 201 Figure 115: ODT During READs .................................................................................................................... 203 Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 205 Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 207 Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 209 Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 211 Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 211 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM Features List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18 Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20 Table 5: Absolute Maximum Ratings .............................................................................................................. 26 Table 6: DDR3 Input/Output Capacitance ...................................................................................................... 27 Table 7: Thermal Characteristics .................................................................................................................... 28 Table 8: Timing Parameters Used for I DD Measurements – Clock Units ............................................................ 30 Table 9: I DD0 Measurement Loop ................................................................................................................... 31 Table 10: I DD1 Measurement Loop .................................................................................................................. 32 Table 11: I DD Measurement Conditions for Power-Down Currents ................................................................... 33 Table 12: I DD2N and I DD3N Measurement Loop ................................................................................................ 34 Table 13: I DD2NT Measurement Loop .............................................................................................................. 34 Table 14: I DD4R Measurement Loop ................................................................................................................ 35 Table 15: I DD4W Measurement Loop ............................................................................................................... 36 Table 16: I DD5B Measurement Loop ................................................................................................................ 37 Table 17: I DD Measurement Conditions for I DD6, I DD6ET, and I DD8 .................................................................... 38 Table 18: I DD7 Measurement Loop .................................................................................................................. 39 Table 19: I DD Maximum Limits – Die Rev D ..................................................................................................... 41 Table 20: I DD Maximum Limits – Die Rev H .................................................................................................... 42 Table 21: I DD Maximum Limits – Die Rev J, M ................................................................................................. 43 Table 22: I DD Maximum Limits – Die Rev K ..................................................................................................... 43 Table 23: DC Electrical Characteristics and Operating Conditions ................................................................... 45 Table 24: DC Electrical Characteristics and Input Conditions .......................................................................... 45 Table 25: Input Switching Conditions ............................................................................................................. 46 Table 26: Control and Address Pins ................................................................................................................ 48 Table 27: Clock, Data, Strobe, and Mask Pins .................................................................................................. 48 Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 49 Table 29: Allowed Time Before Ringback ( t DVAC) for CK - CK# and DQS - DQS# ............................................... 51 Table 30: Single-Ended Input Slew Rate Definition .......................................................................................... 52 Table 31: Differential Input Slew Rate Definition ............................................................................................. 54 Table 32: On-Die Termination DC Electrical Characteristics ............................................................................ 55 Table 33: R TT Effective Impedances ................................................................................................................ 56 Table 34: ODT Sensitivity Definition .............................................................................................................. 57 Table 35: ODT Temperature and Voltage Sensitivity ........................................................................................ 57 Table 36: ODT Timing Definitions .................................................................................................................. 58 Table 37: Reference Settings for ODT Timing Measurements ........................................................................... 58 Table 38: 34 Ohm Driver Impedance Characteristics ....................................................................................... 62 Table 39: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ....................................................... 63 Table 40: 34 Ohm Driver I OH/I OL Characteristics: V DD = V DDQ = 1.5V ................................................................ 63 Table 41: 34 Ohm Driver I OH/I OL Characteristics: V DD = V DDQ = 1.575V ............................................................. 63 Table 42: 34 Ohm Driver I OH/I OL Characteristics: V DD = V DDQ = 1.425V ............................................................. 64 Table 43: 34 Ohm Output Driver Sensitivity Definition .................................................................................... 64 Table 44: 34 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 64 Table 45: 40 Ohm Driver Impedance Characteristics ....................................................................................... 65 Table 46: 40 Ohm Output Driver Sensitivity Definition .................................................................................... 65 Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 66 Table 48: Single-Ended Output Driver Characteristics ..................................................................................... 67 Table 49: Differential Output Driver Characteristics ........................................................................................ 68 Table 50: Single-Ended Output Slew Rate Definition ....................................................................................... 70 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 5 and 6: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 7: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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