2Gb: x4, x8, x16 DDR3 SDRAM - Micron

Figure 78: Method for Calculating t LZ and t HZ
t HZDQS, t HZDQ
Figure 79: t RPRE Timing
T1
T2
t HZDQS, t HZDQ end point = 2 × T1 - T2
V OH - xmV
V OH - 2xmV
V OL + 2xmV
V OL + xmV
V TT + 2xmV
V TT + xmV
V TT - xmV
V TT - 2xmV
T1
T2
t LZDQS, t LZDQ
t LZDQS, t LZDQ begin point = 2 × T1 - T2
Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at t DQSCK (MIN) or t DQSCK
(MAX). Instead, the rising strobe edge can vary between t DQSCK (MIN) and t DQSCK
(MAX).
2. The DQS HIGH pulse width is defined by t QSH, and the DQS LOW pulse width is defined
by t QSL. Likewise, t LZDQS (MIN) and t HZDQS (MIN) are not tied to t DQSCK (MIN) (early
strobe case), and t LZDQS (MAX) and t HZDQS (MAX) are not tied to t DQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by t RPRE (MIN). The minimum
pulse width of the READ postamble is defined by t RPST (MIN).
CK
CK#
DQS
Single-ended signal provided
as background information
DQS#
DQS - DQS#
T1
t RPRE begins
Resulting differential
signal relevant for
t RPRE specification
t C
t A
Single-ended signal provided
as background information
t RPRE
t B
2Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
t D
T2
t RPRE ends
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice.
� 2006 Micron Technology, Inc. All rights reserved.
V TT
V TT
V TT
0V