2Gb: x4, x8, x16 DDR3 SDRAM - Micron

Data Setup, Hold, and Derating
2Gb: x4, x8, x16 DDR3 SDRAM
Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values (see Table 65 (page 105); values come from Table
57 (page 77)) to the �tDS and �tDH derating values (see Table 66 (page 106)), respectively.
Example: tDS (total setup time) = tDS (base) + �tDS. For a valid transition, the
input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 70
(page 109)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transition),
a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC). For slew rates that fall between the values listed in Table 67 (page 106), the
derating values may obtained by linear interpolation.
Setup ( tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup ( tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for
derating value (see Figure 36 (page 110)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 38 (page 112)).
Hold ( tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold ( tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value (see Figure 37 (page 111)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating value
(see Figure 39 (page 113)).
Table 65: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Symbol 800 1066 1333 1600 1866 2133 Unit Reference
tDS (base) AC175 75 25 – – – – ps VIH(AC)/VIL(AC) t DS (base) AC150 125 75 30 10 – – ps VIH(AC)/V IL(AC)
t DS (base) AC135 165 115 60 40 68 53 ps VIH(AC)/V IL(AC)
tDH (base) DC100 150 100 65 45 70 55 ps VIH(DC)/VIL(DC) Slew Rate Referenced 1 1 1 1 2 2 V/ns
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice.
� 2006 Micron Technology, Inc. All rights reserved.