2Gb: x4, x8, x16 DDR3 SDRAM - Micron

Table 16: I DD5B Measurement Loop
CK, CK#
Toggling
CKE
Static HIGH
Sub-Loop
Cycle
Number
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – I DD Specifications and Conditions
Command
CS#
RAS#
CAS#
WE#
0 0 REF 0 0 0 1 0 0 0 0 0 0 0 –
1 D 1 0 0 0 0 0 0 0 0 0 0 –
1a
2
3
D
D#
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
F
0
0
–
–
4 D# 1 1 1 1 0 0 0 0 0 F 0 –
1b 5–8 Repeat sub-loop 1a, use BA[2:0] = 1
1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2
1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3
1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4
1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5
1g 25–28 Repeat sub-loop 1a, use BA[2:0] = 6
1h 29–32 Repeat sub-loop 1a, use BA[2:0] = 7
2 33–nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed
Notes: 1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
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2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data