2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – I DD Specifications and Conditions Electrical Specifications – I DD Specifications and Conditions Within the following IDD measurement tables, the following definitions and conditions are used, unless stated otherwise: • LOW: VIN � V IL(AC)max; HIGH: VIN � V IH(AC)min. • Midlevel: Inputs are VREF = VDD/2. • RON set to RZQ/7 (34�� • RTT,nom set to RZQ/6 (40�� • RTT(WR) set to RZQ/2 (120�� • QOFF is enabled in MR1. • ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR)). • TDQS is disabled in MR1. • External DQ/DQS/DM load resistor is 25� to VDDQ/2. • Burst lengths are BL8 fixed. • AL equals 0 (except in IDD7). • IDD specifications are tested after the device is properly initialized. • Input slew rate is specified by AC parametric test conditions. • Optional ASR is disabled. • Read burst type uses nibble sequential (MR0[3] = 0). • Loop patterns must be executed at least once before current measurements begin. Table 8: Timing Parameters Used for I DD Measurements – Clock Units DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 IDD -25E -25 -187E -187 -15E -15 -125E -125 -107 -093 Parameter 5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 13-13-13 14-14-14 Unit tCK (MIN) IDD 2.5 1.875 1.5 1.25 1.071 0.938 ns CL IDD 5 6 7 8 9 10 10 11 13 14 CK tRCD (MIN) IDD 5 6 7 8 9 10 10 11 13 14 CK tRC (MIN) IDD 20 21 27 28 33 34 38 39 45 50 CK tRAS (MIN) IDD 15 15 20 20 24 24 28 28 32 36 CK tRP (MIN) 5 6 7 8 9 10 10 11 13 14 CK tFAW x4, x8 16 16 20 20 20 20 24 24 26 27 CK x16 20 20 27 27 30 30 32 32 33 38 CK tRRD x4, x8 4 4 4 4 4 4 5 5 5 6 CK IDD x16 4 4 6 6 5 5 6 6 6 7 CK tRFC 1Gb 44 44 59 59 74 74 88 88 103 118 CK 2Gb 64 64 86 86 107 107 128 128 150 172 CK 4Gb 104 104 139 139 174 174 208 208 243 279 CK 8Gb 140 140 187 187 234 234 280 280 328 375 CK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Table 9: I DD0 Measurement Loop CK, CK# Toggling CKE Static HIGH Sub- Loop Cycle Number 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – I DD Specifications and Conditions Command CS# RAS# CAS# WE# 0 ACT 0 0 1 1 0 0 0 0 0 0 0 – 1 D 1 0 0 0 0 0 0 0 0 0 0 – 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 D# 1 1 1 1 0 0 0 0 0 0 0 – 4 D# 1 1 1 1 0 0 0 0 0 0 0 – Repeat cycles 1 through 4 until nRAS - 1; truncate if needed nRAS PRE 0 0 1 0 0 0 0 0 0 0 0 – 0 nRC ACT Repeat cycles 1 through 4 until nRC - 1; truncate if needed 0 0 1 1 0 0 0 0 0 F 0 – nRC + 1 D 1 0 0 0 0 0 0 0 0 F 0 – nRC + 2 D 1 0 0 0 0 0 0 0 0 F 0 – nRC + 3 D# 1 1 1 1 0 0 0 0 0 F 0 – nRC + 4 D# 1 1 1 1 0 0 0 0 0 F 0 – Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed nRC + nRAS PRE 0 0 1 0 0 0 0 0 0 F 0 – 1 2 × nRC Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1; truncate if needed Repeat sub-loop 0, use BA[2:0] = 1 2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. Only selected bank (single) active. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29: Figure 12: Thermal Measurement Poin
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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