2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 CK# CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Address Valid DQS, DQS# ODTLcnw ODTLon WL ODTLcwn4 T10 T11 Command NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ODT R TT DQ ODTH4 t ADC (MAX) t AON (MIN) R TT(WR) DI n DI n + 1 DI n + 2 DI n + 3 ODTLoff t ADC (MIN) R TT,nom t ADC (MAX) Transitioning t AOF (MIN) t AOF (MAX) Don’t Care Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R TT,nom and R TT(WR) are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 CK# CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Address Valid DQS, DQS# ODTLcnw ODTLon WL ODTLcwn4 T10 T11 Command NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ODT R TT DQ ODTH4 t ADC (MAX) t AON (MIN) DI n ODTLoff R TT(WR) DI n + 1 DI n + 2 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT DI n + 3 t AOF (MIN) t AOF (MAX) Transitioning Don’t Care Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R TT,nom can be either enabled or disabled. If disabled, ODT can remain HIGH. R TT(WR) is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Synchronous ODT Mode ODT Latency and Posted ODT Timing Parameters 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT,nom or RTT(WR) is enabled. Based on the power-down definition, these modes are: • Any bank active with CKE HIGH • Refresh mode with CKE HIGH • Idle mode with CKE HIGH • Active power-down mode (regardless of MR0[12]) • Precharge power-down mode if DLL is enabled by MR0[12] during precharge powerdown In synchronous ODT mode, RTT turns on ODTLon clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 91 (page 200)). The ODT latency is tied to the WRITE latency (WL) by ODTLon = WL - 2 and ODTLoff = WL - 2. Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The device’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL + AL - 2. Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff, ODTH4, ODTH8, tAON, and tAOF. The minimum RTT turn-on time ( tAON [MIN]) is the point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time ( tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTLon. The minimum RTT turn-off time ( tAOF [MIN]) is the point at which the device starts to turn off ODT resistance. The maximum RTT turn off time ( tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured from ODTLoff. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 114 (page 201)). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
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Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
Page 195 and 196: Table 89: Mode Registers for R TT(W
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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