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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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PDF: 09005aef826aaadc<br />

<strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />

<strong>2Gb</strong>_<strong>DDR3</strong>_<strong>SDRAM</strong>.pdf – Rev. P 2/12 EN 174 � 2006 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />

Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF)<br />

CK#<br />

CK<br />

Command 1<br />

Address 3<br />

DQS, DQS#<br />

DQ 4<br />

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9<br />

t WPRE<br />

T10 T11<br />

WRITE NOP<br />

NOP NOP<br />

NOP NOP<br />

NOP NOP NOP NOP NOP NOP<br />

READ<br />

Valid<br />

t BL = 4 clocks<br />

t WPST<br />

DI<br />

n<br />

DI<br />

n + 1<br />

DI<br />

n + 2<br />

DI<br />

n + 3<br />

WL = 5 RL = 5<br />

t WTR 2<br />

Indicates break<br />

in time scale<br />

Transitioning Data<br />

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.<br />

2. t WTR controls the WRITE-to-READ delay to the same device and starts after t BL.<br />

3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ<br />

command at Tn.<br />

4. DI n = data-in for column n.<br />

5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).<br />

Tn<br />

Valid<br />

Don’t Care<br />

<strong>2Gb</strong>: <strong>x4</strong>, <strong>x8</strong>, <strong>x16</strong> <strong>DDR3</strong> <strong>SDRAM</strong><br />

WRITE Operation

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