2Gb: x4, x8, x16 DDR3 SDRAM - Micron

More documents

Recommendations

Info

Table 25: Input Switching Conditions 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC 4. V REFDQ(DC) may transition to V REFDQ(SR) and back to V REFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent. DDR3-800 DDR3-1333 DDR3-1866 Parameter/Condition Symbol DDR3-1066 DDR3-1600 DDR3-2133 Unit Command and Address Input high AC voltage: Logic 1 @ 175mV VIH(AC175)min 175 175 – mV Input high AC voltage: Logic 1 @ 150mV VIH(AC150)min 150 150 – mV Input high AC voltage: Logic 1 @ 135 mV VIH(AC135)min – – 135 mV Input high AC voltage: Logic 1 @ 125 mV VIH(AC125)min – – 125 mV Input high DC voltage: Logic 1 @ 100 mV VIH(DC100)min 100 100 100 mV Input low DC voltage: Logic 0 @ –100mV VIL(DC100)max –100 –100 –100 mV Input low AC voltage: Logic 0 @ –125mV VIL(AC125)max – – –125 mV Input low AC voltage: Logic 0 @ –135mV VIL(AC135)max – – –135 mV Input low AC voltage: Logic 0 @ –150mV VIL(AC150)max –150 –150 – mV Input low AC voltage: Logic 0 @ –175mV VIL(AC175)max DQ and DM –175 –175 – mV Input high AC voltage: Logic 1 VIH(AC175)min 175 – – mV Input high AC voltage: Logic 1 VIH(AC150)min 150 150 – mV Input high AC voltage: Logic 1 VIH(AC135)min – – 135 mV Input high DC voltage: Logic 1 VIH(DC100)min 100 100 100 mV Input low DC voltage: Logic 0 VIL(DC100)max –100 –100 –100 mV Input low AC voltage: Logic 0 VIL(AC135)max – – –135 mV Input low AC voltage: Logic 0 VIL(AC150)max –150 –150 – mV Input low AC voltage: Logic 0 VIL(AC175)max –175 – – mV Notes: 1. All voltages are referenced to V REF. V REF is V REFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. V REF is V REFDQ for DQ and DM inputs. 2. Input setup timing parameters ( t IS and t DS) are referenced at V IL(AC)/V IH(AC), not V REF(DC). 3. Input hold timing parameters ( t IH and t DH) are referenced at V IL(DC)/V IH(DC), not V REF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 5. When two V IH(AC) values (and two corresponding V IL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other V IH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: V IH(AC175),min and V IH(AC150),min (corresponding V IL(AC175),min and V IL(AC150),min). For DDR3-800, the address/ command inputs must use either V IH(AC175),min with t IS(AC175) of 200ps or V IH(AC150),min with t IS(AC150) of 350ps; independently, the data inputs must use either V IH(AC175),min with t DS(AC175) of 75ps or V IH(AC150),min with t DS(AC150) of 125ps. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Figure 13: Input Signal 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V Minimum V IL and V IH levels V IH(AC) V IH(DC) V IL(DC) V IL(AC) 1.90V 1.50V 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V 0.0V –0.40V Note: 1. Numbers in diagrams reflect nominal values. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC V IL and V IH levels with ringback V DDQ + 0.4V narrow pulse width V DDQ V IH(AC) V IH(DC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise V IL(DC) V IL(AC) V SS V SS - 0.4V narrow pulse width PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45: Electrical Specifications - DC and
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98:
2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100:
Table 62: Derating Values for t IS/
Page 101 and 102:
Figure 32: Nominal Slew Rate and t
Page 103 and 104:
Figure 34: Tangent Line for t IS (C
Page 105 and 106:
Data Setup, Hold, and Derating 2Gb:
Page 107 and 108:
Table 68: Derating Values for t DS/
Page 109 and 110:
2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112:
Figure 37: Nominal Slew Rate for t
Page 113 and 114:
Figure 39: Tangent Line for t DH (D
Page 115 and 116:
2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118:
Commands DESELECT NO OPERATION ZQ C
Page 119 and 120:
PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122:
DLL Disable Mode • All other self
Page 123 and 124:
Figure 42: DLL Disable Mode to DLL
Page 125 and 126:
Input Clock Frequency Change 2Gb: x
Page 127 and 128:
Write Leveling Figure 45: Write Lev
Page 129 and 130:
Write Leveling Procedure 2Gb: x4, x
Page 131 and 132:
Write Leveling Mode Exit Procedure
Page 133 and 134:
Figure 48: Initialization Sequence
Page 135 and 136:
Figure 50: MRS to nonMRS Command Ti
Page 137 and 138:
Table 77: Burst Order Burst Length
Page 139 and 140:
Mode Register 1 (MR1) Figure 53: Mo
Page 141 and 142:
On-Die Termination (ODT) WRITE LEVE
Page 143 and 144:
Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146:
SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148:
Figure 58: MPR Block Diagram Memory
Page 149 and 150:
PDF: 09005aef826aaadc Micron Techno
Page 151 and 152:
Page 153 and 154:
MPR Read Predefined Pattern The pre
Page 155 and 156:
ACTIVATE Operation Before any READ
Page 157 and 158:
READ Operation Figure 66: READ Late
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166:
Figure 77: Data Strobe Timing - REA
Page 167 and 168:
Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170:
Figure 81: t WPRE Timing Figure 82:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178:
Figure 93: Data Input Timing DQS, D
Page 179 and 180:
Figure 94: Self Refresh Entry/Exit
Page 181 and 182:
Power-Down Mode Power-down is synch
Page 183 and 184:
Figure 95: Active Power-Down Entry
Page 185 and 186:
Figure 98: Power-Down Entry After R
Page 187 and 188:
Figure 102: ACTIVATE to Power-Down
Page 189 and 190:
RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192:
On-Die Termination (ODT) Figure 107
Page 193 and 194:
Dynamic ODT Dynamic ODT Special Use
Page 195 and 196:
Table 89: Mode Registers for R TT(W
Page 197 and 198:
Page 199 and 200:
Synchronous ODT Mode ODT Latency an
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
show all

2Gb: x4, x8, x16 DDR3 SDRAM - Micron

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?