2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Table 20: I DD Maximum Limits – Die Rev H 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – I DD Specifications 5. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C � T C � +85°C: 5a. When T C < 0°C: I DD2P0, I DD2P1 and I DD3P must be derated by 4%; I DD4R and I DD4W must be derated by 2%; and I DD6, I DD6ET and I DD7 must be derated by 7%. 5b. When T C > 85°C: I DD0, I DD1, I DD2N, I DD2NT, I DD2Q, I DD3N, I DD3P, I DD4R, I DD4W, and I DD5B must be derated by 2%; and I DD2Px must be derated by 30%. IDD Speed Bin Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit Notes IDD0 All 70 75 80 88 mA 1, 2 IDD1 All 90 95 100 108 mA 1, 2 IDD2P0 (Slow) All 12 12 12 14 mA 1, 2 IDD2P1 (Fast) All 30 35 40 48 mA 1, 2 IDD2Q All 35 40 45 53 mA 1, 2 IDD2N All 37 42 47 55 mA 1, 2 IDD2NT All 45 50 55 63 mA 1, 2 IDD3P All 40 45 50 58 mA 1, 2 IDD3N All 45 50 55 63 mA 1, 2 IDD4R x4 115 130 145 165 mA 1, 2 x8 130 145 160 180 mA IDD4W x4 115 130 145 165 mA 1, 2 x8 130 145 160 180 mA IDD5B All 185 190 195 205 mA 1, 2 IDD6 All 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 mA 2, 4 IDD7 All 230 245 260 280 mA 1, 2 IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2 Notes: 1. T C = +85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C MAX = +85°C. 4. T C = +85°C; ASR and ODT are disabled; SRT is enabled. 5. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C � T C � +85°C: 5a. When T C < 0°C: I DD2P0, I DD2P1 and I DD3P must be derated by 4%; I DD4R and I DD4W must be derated by 2%; and I DD6, I DD6ET and I DD7 must be derated by 7%. 5b. When T C > +85°C: I DD0, I DD1, I DD2N, I DD2NT, I DD2Q, I DD3N, I DD3P, I DD4R, I DD4W, and I DD5B must be derated by 2%; and I DD2Px must be derated by 30%. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Table 21: I DD Maximum Limits – Die Rev J, M Speed Bin IDD Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit Notes IDD0 All 60 65 70 75 mA 1, 2 IDD1 All 70 75 80 85 mA 1, 2 IDD2P0 (Slow) All 12 12 12 12 mA 1, 2 IDD2P1 (Fast) All 27 32 37 42 mA 1, 2 IDD2Q All 30 35 40 45 mA 1, 2 IDD2N All 33 38 43 48 mA 1, 2 IDD2NT All 35 40 45 50 mA 1, 2 IDD3P All 40 45 50 55 mA 1, 2 IDD3N All 45 50 55 60 mA 1, 2 IDD4R x4 115 126 141 156 mA 1, 2 x8 130 141 156 171 mA IDD4W x4 100 115 130 145 mA 1, 2 x8 115 130 145 160 mA IDD5B All 185 190 195 200 mA 1, 2 IDD6 All 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 mA 2, 4 IDD7 All 210 225 240 255 mA 1, 2 IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2 Notes: 1. T C = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C MAX = 85°C. 4. T C = 85°C; ASR and ODT are disabled; SRT is enabled. 5. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C � T C � +85°C: Table 22: I DD Maximum Limits – Die Rev K 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – I DD Specifications 5a. When T C < 0°C: I DD2P0, I DD2P1 and I DD3P must be derated by 4%; I DD4R and I DD4W must be derated by 2%; and I DD6, I DD6ET and I DD7 must be derated by 7%. 5b. When T C > 85°C: I DD0, I DD1, I DD2N, I DD2NT, I DD2Q, I DD3N, I DD3P, I DD4R, I DD4W, and I DD5B must be derated by 2%; and I DD2Px must be derated by 30%. IDD Speed Bin Widt h DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit Notes IDD0 x4, x8 39 41 42 43 46 mA 1, 2 x16 46 48 49 51 55 mA IDD1 x4 46 50 52 55 57 mA 1, 2 x8 50 54 56 58 60 mA x16 62 67 69 72 75 mA PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41: Electrical Characteristics - I DD S
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 85 and 86: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 93 and 94:
PDF: 09005aef826aaadc Micron Techno
Page 95 and 96:
2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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