2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 200 � 2006 Micron Technology, Inc. All rights reserved. Table 91: Synchronous ODT Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Unit ODTLon ODT synchronous turn-on delay ODT registered HIGH RTT(ON) ± tAON CWL + AL - 2 tCK ODTLoff ODT synchronous turn-off delay ODT registered HIGH RTT(OFF) ± tAOF CWL +AL - 2 tCK ODTH4 ODT minimum HIGH time after ODT ODT registered HIGH or write regis- ODT registered LOW 4 assertion or WRITE (BC4) tration with ODT HIGH tCK tCK ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTLon completion tAOF ODT turn-off relative to ODTLoff completion Figure 113: Synchronous ODT CK# CK CKE ODT R TT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 AL = 3 ODTH4 (MIN) ODTLon = CWL + AL - 2 Completion of ODTLon R TT(ON) See Table 57 (page 77) Completion of ODTLoff R TT(OFF) 0.5 t CK ± 0.2 t CK t CK t AON (MIN) t AON (MAX) AL = 3 T10 T11 T12 T13 T14 T15 ODTLoff = CWL + AL - 2 R TT,nom Note: 1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. R TT,nom is enabled. CWL - 2 Transitioning t AOF (MIN) t AOF (MAX) Don’t Care ps 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode
PDF: 09005aef826aaadc Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 201 � 2006 Micron Technology, Inc. All rights reserved. Figure 114: Synchronous ODT (BC4) CK# CK CKE Command ODT R TT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 t AON (MAX) t AOF (MIN) T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ODTH4 ODTLon = WL - 2 ODTH4 (MIN) ODTLoff = WL - 2 t AON (MIN) R TT,nom ODTH4 ODTLon = WL - 2 t AOF (MAX) t AON (MIN) t AON (MAX) ODTLoff = WL - 2 R TT,nom Transitioning t AOF (MIN) t AOF (MAX) Don’t Care Notes: 1. WL = 7. R TT,nom is enabled. R TT(WR) is disabled. 2. ODT must be held HIGH for at least ODTH4 after assertion (T1). 3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). 4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
Page 195 and 196: Table 89: Mode Registers for R TT(W
Page 199: Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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