2Gb: x4, x8, x16 DDR3 SDRAM - Micron

2Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 187
Figure 104: MRS Command to Power-Down Entry ......................................................................................... 188
Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 188
Figure 106: RESET Sequence ......................................................................................................................... 190
Figure 107: On-Die Termination ................................................................................................................... 191
Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 196
Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 196
Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 197
Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 198
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 198
Figure 113: Synchronous ODT ...................................................................................................................... 200
Figure 114: Synchronous ODT (BC4) ............................................................................................................. 201
Figure 115: ODT During READs .................................................................................................................... 203
Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 205
Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 207
Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 209
Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 211
Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 211
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2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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