2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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ODT Resistors Table 33: R TT Effective Impedances 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Table 33 (page 56) provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what RTT is targeted to provide: • RTT �� is made up of RTT120(PD240) and RTT120(PU240) • RTT �� is made up of RTT60(PD120) and RTT60(PU120) • RTT �� is made up of RTT40(PD80) and RTT40(PU80) • RTT �� is made up of RTT30(PD60) and RTT30(PU60) • RTT �� is made up of RTT20(PD40) and RTT20(PU40) MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Unit 0, 1, 0 �� RTT120(PD240) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.9 1.0 1.4 RZQ/1 RTT120(PU240) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.6 1.0 1.1 RZQ/1 �� VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0, 0, 1 �� RTT60(PD120) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.9 1.0 1.4 RZQ/2 RTT60(PU120) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.6 1.0 1.1 RZQ/2 �� VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0, 1, 1 �� RTT40(PD80) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.9 1.0 1.4 RZQ/3 RTT40(PU80) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.6 1.0 1.1 RZQ/3 �� VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1, 0, 1 �� RTT30(PD60) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.9 1.0 1.4 RZQ/4 RTT30(PU60) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.6 1.0 1.1 RZQ/4 �� VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Table 33: R TT Effective Impedances (Continued) MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Unit 1, 0, 0 �� RTT20(PD40) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.9 1.0 1.4 RZQ/6 RTT20(PU40) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.6 1.0 1.1 RZQ/6 �� VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 ODT Sensitivity Table 34: ODT Sensitivity Definition Note: 1. Values assume an RZQ of 240�� If either the temperature or voltage changes after I/O calibration, then the tolerance limits listed in Table 32 (page 55) and Table 33 can be expected to widen according to Table 34 and Table 35 (page 57). Symbol Min Max Unit RTT 0.9 - dRTTdT × |DT| - dRTTdV × |DV| 1.6 + dRTTdT × |DT| + dRTTdV × |DV| RZQ/(2, 4, 6, 8, 12) ODT Timing Definitions Note: 1. �T = T - T(@ calibration), �V = V DDQ - V DDQ(@ calibration) and V DD = V DDQ. Table 35: ODT Temperature and Voltage Sensitivity 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Change Min Max Unit dRTTdT 0 1.5 %/°C dRTTdV 0 0.15 %/mV Note: 1. �T = T - T(@ calibration), �V = V DDQ - V DDQ(@ calibration) and V DD = V DDQ. ODT loading differs from that used in AC timing measurements. The reference load for ODT timings is shown in Figure 22. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off asynchronously, and another defines when ODT turns on or off dynamically. Table 36 outlines and provides definition and measurement references settings for each parameter (see Table 37 (page 58)). ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance begins to turn off. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 5 and 6: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55: ODT Characteristics Figure 21: ODT
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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