2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
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SRT versus ASR<br />
<strong>2Gb</strong>: <strong>x4</strong>, <strong>x8</strong>, <strong>x16</strong> <strong>DDR3</strong> <strong>SDRAM</strong><br />
Mode Register 2 (MR2)<br />
If the normal TC limit of 85°C is not exceeded, then neither SRT nor ASR is required, and<br />
both can be disabled throughout operation. However, if the extended temperature option<br />
of 95°C is needed, the user is required to provide a 2x refresh rate during manual<br />
refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the<br />
2x rate.<br />
SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is<br />
performed at the 2x refresh rate regardless of the case temperature.<br />
ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. However,<br />
while in self refresh mode, ASR enables the refresh rate to automatically adjust between<br />
1x and 2x over the supported temperature range. One other disadvantage of ASR<br />
is the DRAM cannot always switch from a 1x to 2x refresh rate at an exact TC of 85°C.<br />
Although the DRAM will support data integrity when it switches from a 1x to 2x refresh<br />
rate, it may switch at a temperature lower than 85°C.<br />
Since only one mode is necessary, SRT and ASR cannot be enabled at the same time.<br />
Dynamic On-Die Termination (ODT)<br />
The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled<br />
when a value is selected for the dynamic ODT resistance RTT(WR). This new <strong>DDR3</strong><br />
<strong>SDRAM</strong> feature enables the ODT termination resistance value to change without issuing<br />
an MRS command, essentially changing the ODT termination on-the-fly.<br />
With dynamic ODT (RTT(WR)) enabled, the DRAM switches from nominal ODT (RTT,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst, and subsequently switches<br />
back to normal ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled,<br />
the RTT,nom value will be High-Z. Special timing parameters must be adhered to<br />
when dynamic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcwn4, ODTLcwn8, ODTH4,<br />
ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If normal ODT (RTT,nom) is disabled,<br />
dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent<br />
of one another. Dynamic ODT is not available during write leveling mode, regardless<br />
of the state of ODT (RTT,nom). For details on dynamic ODT operation, refer to<br />
On-Die Termination (ODT) (page 191).<br />
PDF: 09005aef826aaadc<br />
<strong>2Gb</strong>_<strong>DDR3</strong>_<strong>SDRAM</strong>.pdf – Rev. P 2/12 EN 145 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
� 2006 <strong>Micron</strong> Technology, Inc. All rights reserved.