2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row addressing 32K (A[14:0]) 32K (A[14:0]) 16K (A[13:0]) Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) Column addressing 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Page size 1KB 1KB 2KB Figure 1: DDR3 Part Numbers Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16 Example Part Number: MT41J256M8JE-125:M - : MT41J Configuration Package Speed Revision 512M4 256M8 128M16 Package 78-ball 9mm x 11.5mm FBGA HX 78-ball 8mm x 10.5mm FBGA DA 96-ball 9mm x 14mm FBGA HA 96-ball 8mm x 14mm FBGA JT -093 -107 -125 -15E -187E � :D/:H/:K/:M Temperature Commercial Industrial temperature Speed Grade t CK = 0.938ns, CL = 14 t CK = 1.071ns, CL = 13 t CK = 1.25ns, CL = 11 t CK = 1.5ns, CL = 9 t CK = 1.87ns, CL = 7 Revision Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder 2Gb: x4, x8, x16 DDR3 SDRAM Features Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. None IT
2Gb: x4, x8, x16 DDR3 SDRAM Features Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature ............................................................................................................................... 12 General Notes ............................................................................................................................................ 12 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ....................................................................................................................................... 22 Electrical Specifications .................................................................................................................................. 26 Absolute Ratings ......................................................................................................................................... 26 Input/Output Capacitance .......................................................................................................................... 27 Thermal Characteristics .................................................................................................................................. 28 Electrical Specifications – I DD Specifications and Conditions ............................................................................ 30 Electrical Characteristics – I DD Specifications .................................................................................................. 41 Electrical Specifications – DC and AC .............................................................................................................. 45 DC Operating Conditions ........................................................................................................................... 45 Input Operating Conditions ........................................................................................................................ 45 AC Overshoot/Undershoot Specification ..................................................................................................... 48 Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 52 Slew Rate Definitions for Differential Input Signals ...................................................................................... 54 ODT Characteristics ....................................................................................................................................... 55 ODT Resistors ............................................................................................................................................ 56 ODT Sensitivity .......................................................................................................................................... 57 ODT Timing Definitions ............................................................................................................................. 57 Output Driver Impedance ............................................................................................................................... 61 34 Ohm Output Driver Impedance .............................................................................................................. 62 34 Ohm Driver ............................................................................................................................................ 63 34 Ohm Output Driver Sensitivity ................................................................................................................ 64 Alternative 40 Ohm Driver .......................................................................................................................... 65 40 Ohm Output Driver Sensitivity ................................................................................................................ 65 Output Characteristics and Operating Conditions ............................................................................................ 67 Reference Output Load ............................................................................................................................... 69 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 70 Slew Rate Definitions for Differential Output Signals .................................................................................... 71 Speed Bin Tables ............................................................................................................................................ 72 Electrical Characteristics and AC Operating Conditions ................................................................................... 77 Command and Address Setup, Hold, and Derating ........................................................................................... 97 Data Setup, Hold, and Derating ...................................................................................................................... 105 Commands – Truth Tables ............................................................................................................................. 114 Commands ................................................................................................................................................... 117 DESELECT ................................................................................................................................................ 117 NO OPERATION ........................................................................................................................................ 117 ZQ CALIBRATION LONG ........................................................................................................................... 117 ZQ CALIBRATION SHORT .......................................................................................................................... 117 ACTIVATE ................................................................................................................................................. 117 READ ........................................................................................................................................................ 117 WRITE ...................................................................................................................................................... 118 PRECHARGE ............................................................................................................................................. 119 REFRESH .................................................................................................................................................. 119 SELF REFRESH .......................................................................................................................................... 120 DLL Disable Mode ..................................................................................................................................... 121 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 5 and 6: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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