2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb: x4, x8, x16 DDR3 SDRAM Features Input Clock Frequency Change ...................................................................................................................... 125 Write Leveling ............................................................................................................................................... 127 Write Leveling Procedure ........................................................................................................................... 129 Write Leveling Mode Exit Procedure ........................................................................................................... 131 Initialization ................................................................................................................................................. 132 Mode Registers .............................................................................................................................................. 134 Mode Register 0 (MR0) ................................................................................................................................... 135 Burst Length ............................................................................................................................................. 135 Burst Type ................................................................................................................................................. 136 DLL RESET ................................................................................................................................................ 137 Write Recovery .......................................................................................................................................... 137 Precharge Power-Down (Precharge PD) ...................................................................................................... 138 CAS Latency (CL) ....................................................................................................................................... 138 Mode Register 1 (MR1) ................................................................................................................................... 139 DLL ENABLE/DISABLE .............................................................................................................................. 139 Output Drive Strength ............................................................................................................................... 140 OUTPUT ENABLE/DISABLE ...................................................................................................................... 140 TDQS ENABLE .......................................................................................................................................... 140 On-Die Termination (ODT) ........................................................................................................................ 141 WRITE LEVELING ..................................................................................................................................... 141 Posted CAS Additive Latency (AL) ............................................................................................................... 141 Mode Register 2 (MR2) ................................................................................................................................... 143 CAS WRITE Latency (CWL) ........................................................................................................................ 143 AUTO SELF REFRESH (ASR) ....................................................................................................................... 144 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144 SRT versus ASR .......................................................................................................................................... 145 Dynamic On-Die Termination (ODT) ......................................................................................................... 145 Mode Register 3 (MR3) ................................................................................................................................... 146 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146 MPR Functional Description ...................................................................................................................... 147 MPR Address Definitions and Bursting Order .............................................................................................. 148 MPR Read Predefined Pattern .................................................................................................................... 153 MODE REGISTER SET (MRS) Command ........................................................................................................ 153 ZQ CALIBRATION Operation ......................................................................................................................... 154 ACTIVATE Operation ..................................................................................................................................... 155 READ Operation ............................................................................................................................................ 157 WRITE Operation .......................................................................................................................................... 168 DQ Input Timing ....................................................................................................................................... 176 PRECHARGE Operation ................................................................................................................................. 178 SELF REFRESH Operation .............................................................................................................................. 178 Extended Temperature Usage ........................................................................................................................ 180 Power-Down Mode ........................................................................................................................................ 181 RESET Operation ........................................................................................................................................... 189 On-Die Termination (ODT) ............................................................................................................................ 191 Functional Representation of ODT ............................................................................................................. 191 Nominal ODT ............................................................................................................................................ 191 Dynamic ODT ............................................................................................................................................... 193 Dynamic ODT Special Use Case ................................................................................................................. 193 Functional Description .............................................................................................................................. 193 Synchronous ODT Mode ................................................................................................................................ 199 ODT Latency and Posted ODT .................................................................................................................... 199 Timing Parameters .................................................................................................................................... 199 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM Features ODT Off During READs .............................................................................................................................. 202 Asynchronous ODT Mode .............................................................................................................................. 204 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 206 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 208 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 210 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 7 and 8: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 9 and 10: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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