2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
2Gb: x4, x8, x16 DDR3 SDRAM - Micron
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
Input Clock Frequency Change<br />
<strong>2Gb</strong>: <strong>x4</strong>, <strong>x8</strong>, <strong>x16</strong> <strong>DDR3</strong> <strong>SDRAM</strong><br />
Input Clock Frequency Change<br />
When the <strong>DDR3</strong> <strong>SDRAM</strong> is initialized, the clock must be stable during most normal<br />
states of operation. This means that after the clock frequency has been set to the stable<br />
state, the clock period is not allowed to deviate, except for what is allowed by the clock<br />
jitter and spread spectrum clocking (SSC) specifications.<br />
The input clock frequency can be changed from one stable clock rate to another under<br />
two conditions: self refresh mode and precharge power-down mode. It is illegal to<br />
change the clock frequency outside of those two modes. For the self refresh mode condition,<br />
when the <strong>DDR3</strong> <strong>SDRAM</strong> has been successfully placed into self refresh mode and<br />
tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the<br />
clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new<br />
clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode<br />
for the sole purpose of changing the clock frequency, the self refresh entry and exit<br />
specifications must still be met.<br />
The precharge power-down mode condition is when the <strong>DDR3</strong> <strong>SDRAM</strong> is in precharge<br />
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a<br />
logic LOW or RTT,nom and RTT(WR) must be disabled via MR1 and MR2. This ensures<br />
RTT,nom and RTT(WR) are in an off state prior to entering precharge power-down mode,<br />
and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW<br />
before the clock frequency can change. The <strong>DDR3</strong> <strong>SDRAM</strong> input clock frequency is allowed<br />
to change only within the minimum and maximum operating frequency specified<br />
for the particular speed grade ( tCK [AVG] MIN to tCK [AVG] MAX). During the input<br />
clock frequency change, CKE must be held at a stable LOW level. When the input clock<br />
frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge<br />
power-down may be exited. After precharge power-down is exited and tXP has<br />
been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency,<br />
additional MRS commands may need to be issued. During the DLL lock time,<br />
RTT,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is<br />
ready to operate with a new clock frequency.<br />
PDF: 09005aef826aaadc<br />
<strong>2Gb</strong>_<strong>DDR3</strong>_<strong>SDRAM</strong>.pdf – Rev. P 2/12 EN 125 <strong>Micron</strong> Technology, Inc. reserves the right to change products or specifications without notice.<br />
� 2006 <strong>Micron</strong> Technology, Inc. All rights reserved.