2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Table 87: Dynamic ODT Specific Parameters • During DRAM operation without READ or WRITE commands, the termination is controlled. – Nominal termination strength RTT,nom is used. – Termination on/off timing is controlled via the ODT ball and latencies ODTLon and ODTLoff. • When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled. – A latency of ODTLcnw after the WRITE command: termination strength RTT,nom switches to RTT(WR) – A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT(WR) switches back to RTT,nom. – On/off termination timing is controlled via the ODT ball and determined by ODT- Lon, ODTLoff, ODTH4, and ODTH8. – During the tADC transition window, the value of RTT is undefined. ODT is constrained during writes and when dynamic ODT is enabled (see Table 87 (page 194)). ODT timings listed in Table 85 (page 192) also apply to dynamic ODT mode. Symbol Description Begins at Defined to ODTLcnw Change from RTT,nom to RTT(WR) ODTLcwn4 Change from RTT(WR) to RTT,nom (BC4) ODTLcwn8 Change from RTT(WR) to RTT,nom (BL8) Write registration R TT switched from R TT,nom to R TT(WR) Write registration R TT switched from R TT(WR) to R TT,nom Write registration R TT switched from R TT(WR) to R TT,nom Definition for All DDR3 Speed Bins Unit WL - 2 tCK 4 t CK + ODTL off 6 t CK + ODTL off t ADC RTT change skew ODTLcnw completed R TT transition complete 0.5 t CK ± 0.2 t CK t CK Table 88: Mode Registers for R TT,nom MR1 (R TT,nom) 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT M9 M6 M2 RTT,nom (RZQ) RTT,nom (Ohm) RTT,nom Mode Restriction 0 0 0 Off Off n/a 0 0 1 RZQ/4 60 Self refresh 0 1 0 RZQ/2 120 0 1 1 RZQ/6 40 1 0 0 RZQ/12 20 Self refresh, write 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a Note: 1. RZQ = 240�. If R TT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. t CK t CK
Table 89: Mode Registers for R TT(WR) MR2 (R TT(WR)) M10 M9 RTT(WR) (RZQ) RTT(WR) (Ohm) 0 0 Dynamic ODT off: WRITE does not affect RTT,nom 0 1 RZQ/4 60 1 0 RZQ/2 120 1 1 Reserved Reserved Table 90: Timing Diagrams for Dynamic ODT 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT Figure and Page Title Figure 108 (page 196) Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 Figure 109 (page 196) Dynamic ODT: Without WRITE Command Figure 110 (page 197) Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Figure 111 (page 198) Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 Figure 112 (page 198) Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 195 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
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Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
Page 169 and 170: Figure 81: t WPRE Timing Figure 82:
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193: Dynamic ODT Dynamic ODT Special Use
Page 199 and 200: Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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