2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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34 Ohm Output Driver Impedance The 34� driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34� driver only. Its impedance R ON is defined by the value of the external reference resistor RZQ as follows: R ON34 = RZQ/7 (with nominal RZQ = 240��±1%) and is actually 34.3�� Table 38: 34 Ohm Driver Impedance Characteristics 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance MR1[5,1] RON Resistor VOUT Min Nom Max Unit Notes 0,1 �� RON34(PD) 0.2/VDDQ 0.6 1.0 1.1 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.9 1.0 1.4 RZQ/7 RON34(PU) 0.2/VDDQ 0.9 1.0 1.4 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.6 1.0 1.1 RZQ/7 Pull-up/pull-down mismatch (MMPUPD) 0.5/VDDQ –10% n/a 10 % 2 Notes: 1. Tolerance limits assume RZQ of 240��±1% and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage: VDDQ = VDD; VSSQ = VSS). Refer to 34 Ohm Output Driver Sensitivity (page 64) if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 × VDDQ: RON(PU) - RON(PD) MMPUPD = × 100 RON,nom 3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (T C). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
34 Ohm Driver The 34� driver’s current range has been calculated and summarized in Table 40 (page 63) VDD = 1.5V, Table 41 (page 63) for VDD = 1.57V, and Table 42 (page 64) for VDD = 1.42V. The individual pull-up and pull-down resistors RON34(PD) and RON34(PU) are defined as follows: • RON34(PD) = (VOUT)/|IOUT|; RON34(PU) is turned off • RON34(PU) = (VDDQ - VOUT)/|IOUT|; RON34(PD) is turned off Table 39: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Unit RZQ = 240�� 237.6 240 242.4 � RZQ/7 = (240�� 33.9 34.3 34.6 � MR1[5,1] RON Resistor VOUT Min Nom Max Unit 0, 1 �� RON34(PD) 0.2 × VDDQ 20.4 34.3 38.1 � 0.5 × VDDQ 30.5 34.3 38.1 � 0.8 × VDDQ 30.5 34.3 48.5 � RON34(PU) 0.2 × VDDQ 30.5 34.3 48.5 � 0.5 × VDDQ 30.5 34.3 38.1 � 0.8 × VDDQ 20.4 34.3 38.1 � Table 40: 34 Ohm Driver I OH/I OL Characteristics: V DD = V DDQ = 1.5V MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 �� RON34(PD) IOL @ 0.2 × VDDQ 14.7 8.8 7.9 mA IOL @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOL @ 0.8 × VDDQ 39.3 35.0 24.8 mA RON34(PU) IOH @ 0.2 × VDDQ 39.3 35.0 24.8 mA IOH @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOH @ 0.8 × VDDQ 14.7 8.8 7.9 mA Table 41: 34 Ohm Driver I OH/I OL Characteristics: V DD = V DDQ = 1.575V 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 �� RON34(PD) IOL @ 0.2 × VDDQ 15.5 9.2 8.3 mA IOL @ 0.5 × VDDQ 25.8 23 20.7 mA IOL @ 0.8 × VDDQ 41.2 36.8 26 mA RON34(PU) IOH @ 0.2 × VDDQ 41.2 36.8 26 mA IOH @ 0.5 × VDDQ 25.8 23 20.7 mA IOH @ 0.8 × VDDQ 15.5 9.2 8.3 mA PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37 and 38: Table 16: I DD5B Measurement Loop C
Page 39 and 40: Table 18: I DD7 Measurement Loop CK
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61: Output Driver Impedance Figure 26:
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 97 and 98: 2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 99 and 100: Table 62: Derating Values for t IS/
Page 101 and 102: Figure 32: Nominal Slew Rate and t
Page 103 and 104: Figure 34: Tangent Line for t IS (C
Page 105 and 106: Data Setup, Hold, and Derating 2Gb:
Page 107 and 108: Table 68: Derating Values for t DS/
Page 109 and 110: 2Gb: x4, x8, x16 DDR3 SDRAM Data Se
Page 111 and 112: Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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PDF: 09005aef826aaadc Micron Techno
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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