2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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Table 84: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 RTT,nom disabled, ODT off Any valid 2 000 1 RTT,nom disabled, ODT on Any valid except self refresh, read 3 000–101 0 RTT,nom enabled, ODT off Any valid 2 000–101 1 RTT,nom enabled, ODT on Any valid except self refresh, read 3 110 and 111 X RTT,nom reserved, ODT on or off Illegal Table 85: ODT Parameters Notes: 1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 193) when enabled). 2. ODT is enabled and active during most writes for proper termination, but it is not illegal for it to be off during writes. 3. ODT must be disabled during reads. The R TT,nom value is restricted during writes. Dynamic ODT is applicable if enabled. Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1 (MR1) Definition. The RTT,nom termination value applies to the output pins previously mentioned. DDR3 SDRAM supports multiple RTT,nom values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240�. RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is disabled. If RTT,nom is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 88 (page 194)). ODT timings are summarized in Table 85 (page 192), as well as listed in Table 57 (page 77). Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in Synchronous ODT Mode (page 199). Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Unit ODTLon ODT synchronous turn-on delay ODT registered HIGH RTT(ON) ± tAON CWL + AL - 2 tCK ODTLoff ODT synchronous turn-off delay ODT registered HIGH RTT(OFF) ± tAOF CWL + AL - 2 tCK tAONPD ODT asynchronous turn-on delay ODT registered HIGH RTT(ON) 2–8.5 ns tAOFPD ODT asynchronous turn-off delay ODT registered HIGH RTT(OFF) 2–8.5 ns ODTH4 ODT minimum HIGH time after ODT assertion or write (BC4) ODTH8 ODT minimum HIGH time after write (BL8) t AON ODT turn-on relative to ODTLon completion t AOF ODT turn-off relative to ODTLoff completion ODT registered HIGH or write registration with ODT HIGH Write registration with ODT HIGH Completion of ODTLon Completion of ODTLoff 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) ODT registered LOW ODT registered LOW 4 t CK 6 t CK t CK t CK R TT(ON) See Table 57 (page 77) ps R TT(OFF) 0.5 t CK ± 0.2 t CK t CK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Dynamic ODT Dynamic ODT Special Use Case In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT R TT(WR)) enabled, the DRAM switches from nominal ODT R TT,nom) to dynamic ODT R TT(WR)) when beginning a WRITE burst and subsequently switches back to nominal ODT R TT,nom) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below. When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a special use case: the ODT ball can be wired high (via a current limiting resistor preferred) by having RTT,nom disabled via MR1 and RTT(WR) enabled via MR2. This will allow the ODT signal not to have to be routed yet the DRAM can provide ODT coverage during write accesses. When enabling this special use case, some standard ODT spec conditions may be violated: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this would appear to be a problem since RTT(WR) can not be used (should be disabled) and RTT(NOM) should be used. For Write leveling during this special use case, with the DLL locked, then RTT(NOM) maybe enabled when entering Write Leveling mode and disabled when exiting Write Leveling mode. More so, RTT(NOM) must be enabled when enabling Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via same MR1 load if RTT(NOM) is to be used. ODT will turn-on within a delay of ODTLon + tAON + tMOD + 1CK (enabling via MR1) or turn-off within a delay of ODTLoff + tAOF + tMOD + 1CK. As seen in the table below, between the Load Mode of MR1 and the previously specified delay, the value of ODT is uncertain. this means the DQ ODT termination could turn-on and then turn-off again during the period of stated uncertainty. Table 86: Write Leveling with Dynamic ODT Special Case Begin RTT,nom Uncertainty End RTT,nom Uncertainty I/Os RTT,nom Final State MR1 load mode command: ODTLon + Enable Write Leveling and RTT(NOM) tAON + tMOD + 1CK DQS, DQS# Drive RTT,nom value DQs No RTT,nom MR1 load mode command: ODTLoff + Disable Write Leveling and RTT(NOM) tAOFF + tMOD + 1CK DQS, DQS# No RTT,nom DQs No RTT,nom Functional Description The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic ODT is not supported during DLL disable mode so RTT(WR) must be disabled. The dynamic ODT function is described below: • Two RTT values are available—RTT,nom and RTT(WR). – The value for R TT,nom is preselected via MR1[9, 6, 2]. – The value for R TT(WR) is preselected via MR2[10, 9]. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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Page 143 and 144: Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
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Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Page 167 and 168: Figure 80: t RPST Timing CK CK# DQS
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Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191: On-Die Termination (ODT) Figure 107
Page 195 and 196: Table 89: Mode Registers for R TT(W
Page 199 and 200: Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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