2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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WRITE Operation 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed is precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 83 (page 170) through Figure 91 (page 175), auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS following the WRITE latency (WL) clocks later and subsequent data elements will be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS, DQS#) and specified as the WRITE preamble shown in Figure 83 (page 170). The half cycle on DQS following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQS is WL clocks ± tDQSS. Figure 84 (page 171) through Figure 91 (page 175) show the nominal case where tDQSS = 0ns; however, Figure 83 (page 170) includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The data mask occurs on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figure 84 (page 171) and Figure 85 (page 171) show concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 86 (page 172). Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figure 87 (page 172), Figure 88 (page 173), and Figure 89 (page 174)). Data for any WRITE burst may be followed by a subsequent PRECHARGE command, providing tWR has been met, as shown in Figure 90 (page 175) and Figure 91 (page 175). Both tWTR and tWR starting time may vary, depending on the mode register settings (fixed BC4, BL8 versus OTF). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Figure 81: t WPRE Timing Figure 82: t WPST Timing CK CK# DQS - DQS# CK CK# T1 t WPRE begins Resulting differential signal relevant for t WPRE specification DQS - DQS# Resulting differential signal relevant for t WPST specification t WPRE T1 t WPST begins t WPST 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation T2 t WPRE ends T2 t WPST ends PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. 0V V TT V TT 0V
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DDR3 SDRAM MT41J512M4 - 64 Meg x 4
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2Gb: x4, x8, x16 DDR3 SDRAM Feature
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State Diagram Figure 2: Simplified
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2Gb: x4, x8, x16 DDR3 SDRAM Functio
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Figure 4: 256 Meg x 8 Functional Bl
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Figure 7: 96-Ball FBGA - x16 (Top V
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Table 3: 78-Ball FBGA - x4, x8 Ball
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Table 4: 96-Ball FBGA - x16 Ball De
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Figure 9: 78-Ball FBGA - x4, x8 (HX
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Figure 11: 96-Ball FBGA - x16 (JT)
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Input/Output Capacitance Table 6: D
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Figure 12: Thermal Measurement Poin
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Table 9: I DD0 Measurement Loop CK,
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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Table 14: I DD4R Measurement Loop C
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Table 16: I DD5B Measurement Loop C
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Table 18: I DD7 Measurement Loop CK
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Electrical Characteristics - I DD S
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Table 21: I DD Maximum Limits - Die
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Electrical Specifications - DC and
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Figure 13: Input Signal 0.925V 0.85
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Table 28: Differential Input Operat
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Figure 18: Definition of Differenti
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Figure 19: Nominal Slew Rate Defini
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ODT Characteristics Figure 21: ODT
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Table 33: R TT Effective Impedances
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Figure 23: t AON and t AOF Definiti
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Output Driver Impedance Figure 26:
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34 Ohm Driver The 34� driver’s
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Alternative 40 Ohm Driver Table 45:
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Output Characteristics and Operatin
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Figure 28: Differential Output Sign
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Slew Rate Definitions for Different
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Table 53: DDR3-1333 Speed Bins DDR3
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Table 55: DDR3-1866 Speed Bins DDR3
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
Page 117 and 118: Commands DESELECT NO OPERATION ZQ C
Page 119 and 120: PRECHARGE REFRESH 2Gb: x4, x8, x16
Page 121 and 122: DLL Disable Mode • All other self
Page 123 and 124: Figure 42: DLL Disable Mode to DLL
Page 125 and 126: Input Clock Frequency Change 2Gb: x
Page 127 and 128: Write Leveling Figure 45: Write Lev
Page 129 and 130: Write Leveling Procedure 2Gb: x4, x
Page 131 and 132: Write Leveling Mode Exit Procedure
Page 133 and 134: Figure 48: Initialization Sequence
Page 135 and 136: Figure 50: MRS to nonMRS Command Ti
Page 137 and 138: Table 77: Burst Order Burst Length
Page 139 and 140: Mode Register 1 (MR1) Figure 53: Mo
Page 141 and 142: On-Die Termination (ODT) WRITE LEVE
Page 143 and 144: Mode Register 2 (MR2) Figure 55: Mo
Page 145 and 146: SRT versus ASR 2Gb: x4, x8, x16 DDR
Page 147 and 148: Figure 58: MPR Block Diagram Memory
Page 149 and 150: PDF: 09005aef826aaadc Micron Techno
Page 153 and 154: MPR Read Predefined Pattern The pre
Page 155 and 156: ACTIVATE Operation Before any READ
Page 157 and 158: READ Operation Figure 66: READ Late
Page 163 and 164: 2Gb: x4, x8, x16 DDR3 SDRAM READ Op
Page 165 and 166: Figure 77: Data Strobe Timing - REA
Page 167: Figure 80: t RPST Timing CK CK# DQS
Page 175 and 176: Figure 90: WRITE (BL8) to PRECHARGE
Page 177 and 178: Figure 93: Data Input Timing DQS, D
Page 179 and 180: Figure 94: Self Refresh Entry/Exit
Page 181 and 182: Power-Down Mode Power-down is synch
Page 183 and 184: Figure 95: Active Power-Down Entry
Page 185 and 186: Figure 98: Power-Down Entry After R
Page 187 and 188: Figure 102: ACTIVATE to Power-Down
Page 189 and 190: RESET Operation 2Gb: x4, x8, x16 DD
Page 191 and 192: On-Die Termination (ODT) Figure 107
Page 193 and 194: Dynamic ODT Dynamic ODT Special Use
Page 195 and 196: Table 89: Mode Registers for R TT(W
Page 199 and 200: Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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